3D InCites: Unveiled

Today, July 6, 2009, is the day a vision becomes a reality. When I first started Françoise in 3D, I knew it was just the beginning of something much bigger. During the last six months, with the help of Leo Archer, industry colleague, friend, and now full-fledged business partner; and Robert Petrossian, founder of SemiNeedle; this vision has taken shape and form to become 3D InCites a sponsor-supported community forum dedicated to stirring up interest in 3D integration. From now on, that will be the new home of Francoise in 3D, so please bookmark http://www.3dincites.com/ for uninterrupted coverage.

I don’t want to spend a lot of time explaining what this site is. I’d rather you spend your time taking it out for a test drive. You’ll notice we’ve established topic centers focused on the different categories critical to 3D Integration technologies: R&D collaboration; materials; equipment; processes technology; and; design, test and inspection. Tell us what you think. Consider becoming a sponsor. To celebrate this launch, we will post the logos of the first 10 organizations who post comments in their associated topic center for the duration of SEMICON West.

Finally, I'd like to welcome Leo to this space as a fellow blogger in 3D integration trends. Be sure to read Transistions - Part 1, for a full explanation of our vision, concept, and business model. -- F.v.T.

SEMATECH: hitting 3D head-on

At last week’s SEMATECH technology round-up webcast, Sitaram Arkalgud, director of 3D interconnect, made a comment about 3D technologies that, in my opinion, really brought all the issues swirling around it to one vital point. It was this: as a platform, 3D allows a whole other scheme of processes to be considered that don’t enter the realm of possibilities when you’re dealing with a 2D platform.

By now, those of us who regularly attend 3D events can recite the benefits of moving to 3D using TSV—reduced form factor, increased functionality, higher performance, and lower power consumption, reduced cost, etc. Arkalgud expanded on the cost reduction benefit by pointing out that 3D offers the potential for containing costs at device, die wafer, factory and market levels, which could be powerful going forward. He said that even though adding certain steps may additionally add to the cost structure, the benefits will be realized further down the supply chain.

In 2005, when deciding to invest in an R&D program to develop 3D integration using TSV, SEMATECH began by assessing different options, focusing first on materials, via formation, bonding, and integration. To further narrow these options, they focused on cost modeling, performance, risk, and product requirements; benchmarking tools and processes to achieve this. In 2008, the organization really got into the thick of technology development, focusing on the “nuts and bolts of 3D” using 300mm equipment 3D specific tools. The goal of the program, explains Arkalgud, is to have a test bed for member (IDMs, foundries, suppliers, etc.) evaluations.

So far, Arkalgud reports that SEMATECH’s key processes have been:

TSV reactive ion etch: 1 micron vias at a 20:1 aspect ratio using a non-Bosch process on TEL SP UD.

Dielectric liner, barrier, seed layer: TEO/TaN/PVD cu seend using a CSNE toolset.

Void-free via fill: void free Cu via fill using NEXX Stratus

Bonding of wafer or dies: Cu thermocompression wafer-wafer (W2W) bond on 300mm tools.

Working on thinning and handling of wafers/die

3D –specific metrology: IR scanning acoustic microscopy

Specifically addressing issues with thin wafer handling and stresses caused by backside processing and subsequent bonding, Arkalgud notes that the greatest issues still lies with thermal stresses caused by processing conditions, and material requirements for temporary bonding and debonding methodologies. He says that SEMATECH’s 3D program aims to establish standard methodologies with which to evaluate current processes and materials to create its own data that can be compared “apples-to-apples”, rather than rely on data provided by individual suppliers. The organization is currently evaluating 300mm bonding tools to determine which will be most suited to carry out this work.

Additionally, when it comes to addressing thermal issues with 3D integration, Arkalgud says possible solutions involve using dummy TSVs as heat sinks; developing design tools that dynamically detect where hotspots would be and designing accordingly; or even incorporating channels for microfluidic cooling. This is where Arkalgud’s comment came in about 3D schemes offering new possibilities where 2D falls short. Really, when you think about it, at 2D if we attempt to further reduce form factor while increasing functionality and performance in a 2D scheme, we’re going to hit the same roadblocks in thermal management, power consumption, yield management, cost, etc. While 3D may not have all the answers yet, it certainly opens the door to solutions that otherwise can’t be achieved. – F.v.T.

SUSS MicroTec: A 3D Approach

It’s been a few years since I toured the US headquarters of SUSS MicroTec in Waterbury VT, so when general manager, Wilfried Bair invited me out to see their latest toolset developed with 3D integration processes in mind, and get the scoop on the company’s new temporary bonding and debonding system, I jumped at the chance.

Wafer-level packaging, MEMS, and LED have long been the foci of SUSS MicroTec, but as 3D integration and packaging processes emerge as pivotal to the semiconductor industry, SUSS MicroTec has adjusted its strategy. Rather than adapting existing tool sets to also handle 3D integration processes, 3D now tops the priority list, and all 300 mm equipment in development has been optimized with 3D processes in mind first, which in turn benefits the existing markets with higher performing tools. Wilfried Bair, general manager of SUSS MicroTec’s bonder division, and V.P. of business development worldwide, describes this win-win situation: “3D is driving innovation,” he says, and every other market we serve benefits.”

In his book, Handbook of 3D Integration: Technology and Applications of 3D Integrated Circuits, Dr. Phil Garrou, identifies 9 potential process variations for 3D IC stacking involving via formation, (vias first, middle, or last); thinning (on temp. carrier or 3D stack); temporary and/or permanent bonding (face to face or face to back bonding). Regardless of which variations shake out as standard, SUSS MicroTec has tools to cover it from patterning for TSVs (mask aligners and coaters), to bonding and stacking for either wafer-to-wafer die-to-wafer stacking (permanent bonding) as well as temporary bonding and debonding.

By far the most exciting piece of news Bair shared, (and one I had been waiting in anticipation for quite a while) involved the Bonder Division’s flagship platform, the XBC300, which offers a complete line of process modules for permanent and temporary wafer bonding. Of specific interest is the temporary bonding and debonding system that supports several different material processes that exist in the market.

Until the recently announced agreement with 3M, SUSS MicroTec has focused on the work with T-MAT, a German start-up company. To demonstrate the elegant simplicity of the T-MAT process, Bair first walked me through three comparable processes that can be performed on the XBC300, whose modules have been configured for temporary bonding (SC300 - Spin Coat for process integration and simplification; PL300T - Plasma to form release layer; LF300 - Low Force bond).

In Brewer Science's Thermoslide process, the device wafer is flipped face down and temporarily bonded to a carrier wafer that has been first coated with an adhesive by spin-coating and baking. The device wafer is aligned and bonded and backside processing occurs. During the debond process, an electrostatic chuck is secured to the backside of the wafer (now on top) and by applying heat, is slid off the carrier wafer. It is then flipped while still attached to the chuck, cleaned, and then either flipped again and attached to a dicing frame for die-to-wafer stacking; or aligned and permanently bonded for wafer-to-wafer stacking. Bair notes that this process is not easy to do, requires multiple process steps, and is therefore expensive. It also has issues with delamination during the debond step on 300mm wafers.

The 3M process, by comparison, requires only one carrier transfer in the temporary bonding step. In this scenario, both the device wafer and the glass carrier are spin coated with a material; adhesive on the wafer, and a release layer on the carrier. The wafer is then flipped and bonded to the carrier by means of a UV curing step. After backside processing, the debonding processes is simple: the thinned device wafer is flipped and attached to the dicing frame, the release layer is activated by means of a laser to remove the carrier wafer easily, and then the adhesive is peeled away from the device wafer, which is subsequently cleaned and ready for stacking. Bair says this is an easier process, and although there is an additional bonding step, it’s fast and clean and can be done at room temperature.

The T-MAT (shown below) process further simplifies debonding by spincoating a precursor (elastomer) on both the device wafer and carrier wafer in the bonding process, and then using plasma to form the release layer. The device wafer is flipped and temporarily bonded to the carrier wafer. The debond process is simple. Wafers destined for W2W stacking are precision-aligned and permanently bonded. Those destined for D2W stacking are attached to a dicing frame. In either case, debonding is a cold process, and requires only a small gap to be made between the carrier and device wafer so it can be lifted off.



Bair’s philosophy – and therefore the basis of his approach for business development at SUSS MicroTec is simple: Provide the whole infrastructure. Build equipment that is standardized and flexible. When a new process pops up, make sure it can be accommodated. “Customers want bonded wafers, at lowest cost, with highest yield,” says Bair “How we do that is our problem.” Enough said. -- F.v.T.

Today's post is sponsored by

Countdown to SEMICON West 2009

With only 2.5 weeks to go (you're all saying, really? it's that close?) until SEMICON West, I can see the activity building around this year's event. I've already talked about the increased focus on 3D this year. One thing I didn't mention yet are the various awards programs that are happening....or not.

Semi's own Best of the West Awards, launched last year to promote innovation and recognize important product and technology developments in the microelectronics supply chain, is back again for it's second year. The finalists were announced this week, and according to a press release, were selected "based on their financial impact on the industry, engineering or scientific achievement, and/or societal impact." On that list for the second time in two years is Alchimer, this time for it's AquiVia wet depostion technology. Last year, the company's egViaCoat electrografting process for copper seed made the list.

Absent from this year's line-up are both the Attendee's Choice Awards and the Advanced Packaging Awards. Instead, this year Solid State Technology and Advanced Packaging will honor those who have made it through this economic downturn through efforts to "compete, innovate and achieve" by bestowing the Semiconductor Survivor Awards. If you haven't already entered, you have until June 29.

One thing's for certain, people certainly are tapping into ingenuity this year to make the most out of SEMICON West on a tight budget. I think this really says something for the overall existance of the event. I mean, if it wasn't such an icon of the industry, companies would just pull out of it all together, wouldn't they? Maybe SEMI should get an honorary Survivor Award just for that. -- F.v.T.

3D companies address critical areas

It’s only Tuesday, and already, it’s been a productive week for 3D news.

Yesterday, SUSS and 3M announced an agreement in which SUSS becomes an authorized equipment supplier for 3M’s temporary bond and debond process. As such, SUSS’s 300mm wafer bonders will be configured to support 3M’s process and materials. This ties in to SUSS’s 3D strategy, which according to Wilfried Bair, general manager, Wafer Bonder Division, SUSS MicroTec, is to provide “a flexible, modular platform” configurable to customer needs. He recently explained to me that how you debond depends on the materials you bond with. Carrier wafer processes have been used in manufacturing high power devices for years, but the requirements around 3D are different, when you consider that instead of 200mm wafers, you’re potentially dealing with 300mm wafers thinned to 50µm. The fewer the steps, and lower the temperature, the better. So the advantages to the 3M process is that there’s only one carrier wafer step involved, it’s fast, clean, and can be done at room temperature.

Today, Alchimer SA, made a three-fold announcement, leading off with the news that it received its 3rd round of funding in the amount of $10M to expand customer-support programs and pursue new IP development. This is a significant achievement given the current economic climate. Additionally, the company formally welcomed Kathy Cook aboard as business development manager, who brings a solid background from previous positions at SUSS MicroTec, Applied Materials, Millipore, and ULVAC Technologies. (Incidentally Kathy, don’t let them call you “veteran” again in a press release. It makes you sound MUCH older than you are.) Alchimer also announced an agreement with Nagase Ltd., a Tokyo-based marketing firm, to help them meet the demand of the Japanese market.This news, coupled with last week’s announcement that the company had achieved an 80% reduction in cost-of-ownership for its egViaCoat processes indicates that this company is really on to something with this low-cost wet deposition alternative for TSV copper seed.

Lastly, DEK international stepped into the 3D arena, combining efforts with CHAD to incorporate DEK’s thin wafer system with CHAD’s wafer handler, thereby addressing traditional challenges associated with high-speed handling and processing of thinned wafers for emerging 3D packaging, wafer coating and ball placement processes. The companies plan to demonstrate their capabilities during SEMICON West. I look forward to learning more about this at the show.

Individually, these announcements have nothing to do with one another, but collectively, they can be used to illustrate how the industry is addressing some of the remaining critical areas of 3D integration with TSV interconnects. Insulator barrier/ seed, and wafer bonding; — particularly temporary bonding and debonding — and thin wafer handling have been pointed out as areas still needing cost-effective solutions. Looks like we’re making progress. – F.v.T.

3D processes and approaches: stepping stones to market adoption

I recently had one of those moments of clarity that comes from asking different people the same questions and fitting all the varied answers together like a puzzle to come up with the big picture. In this case, the questions had to do with the various approaches being developed to achieve 3D integration using TSVs – namely, via-first, middle and last for via formation; and wafer-to-wafer (W2W) and die-to-wafer (D2W) for device stacking. One thing is for sure, there is no shortage on opinions out there surrounding these issues.

At the risk of oversimplification, I offer up the following analysis; perhaps the best way to understand how 3D integration using TSV will ultimately come together is to see it as a progression – a stepping stone approach. Even though that’s how the questions are often posed – it’s not likely to end up as an either-or situation.

D2W currently achieves better yields than W2W, but once the known-good-die issue is figured out, W2W will be a more cost-effective process because it is done in parallel. Via-middle will most likely be the TSV champion, once design and test tools are available; but until then, some predict that the first products will be built using via-last, which can be done with existing die. It’s a matter of convincing the industry as a whole (and there are still many who remain skeptical that TSV itself is the answer) that overcoming current limitations for W2W and via-middle is a worthy investment.

Regardless of how things shake out, the equipment and materials manufacturers are covering their bases by making sure their tools and chemistries adapt or exist for all possible variations. Because no matter which processes are adopted for volume production, there will always be niche applications that are better suited to the processes that don’t reach volume production. – F.v.T

Are you an oldtimer or a newcomer?

It has nothing to do with age, and everything to do with whether you have the ability to embrace new and exciting things, or whether you deem them unworthy of your time.

When it comes to communication, we live in a rapidly changing world. A couple of years ago, using the Internet as a means of communication was still fairly linear. E-mail and IM were firmly established for two-way communication, but Skype was just starting to be accepted, and social networking for both personal and professional purposes was very much on fringe – used only by the savviest and most trendy adopters of technology; college students, teenagers, rock stars, and other social elite; or professionals looking to build their networks. In the past year that has changed dramatically, as people from all walks of life discover the usefulness of these methods of staying in touch, when used with respect.

I “talk” to lots of people every day – on the phone, via email, Skype, LinkedIn, facebook, in web meetings on SemiNeedle, and finally just a few days ago, on Twitter. As an industry commentator, these have become the tools of my trade. I find them incredibly efficient methods for connecting with colleagues and friends from around the world, as well as for sharing information. I don’t worry that it imposes on my time, because I know how to set an out-of-office email, and how to power down my laptop and cell phone. So I don’t really get when people, especially those in the business of gathering and sharing information, say “I don’t have time for those things.” I think what they’re really saying is, “I don’t have time to learn how they work and incorporate them into my lifestyle”.

In my opinion, if you’re in the communication business, these tools can actually help save both time and money, and are worth the time investment of becoming familiar with them. The truth of the matter is, those teenagers and college students who started using them from the beginning are joining the workforce, which means that over time, they will replace traditional methods of exchanging information. After all, most of them are so easy, even a child can use them…

So which are you, an Oldtimer or a Newcomer? -- F.v.T

3D is hot at SEMICON West

Given the building momentum around 3D integration schemes and the attention it's getting as the semiconductor bright spot, it's no surprise that at this year’s SEMICON West, there are more programs focused on 3D integration technology issues, both on and off-site, than last year. In fact, if you want to plan your itinerary around all things 3D, you can easily fill your schedule.(Trust me on this one, my dance card is overflowing.)

Whet your appetite by joining in the discussion online at the aptly-named, Brightspots 3D IC Forum. Moderated by yours truly, this roundtable discussion will address critical issues surrounding 3D integration from the front-end through the back-end. Discussion opens at 6am PT, on July 6 (looks like I'll be moderating this one in my jammies) and closes July 24. The more people who participate, the more interesting I’m sure it will be, so sign up early and visit often.

SEMI has organized several program events around 3D integration beginning with a Packaging Summit on Tuesday, July 14 from 3:30-5:30, that begs the question: When the Package is the Product, will 3D Integration be the Holy Grail? This summit will address the business side of 3D, discussing how these emerging technologies will overcome cost and time-to-market to find their way into consumer electronic applications. Additionally, Wed. July 15 from 2-4pm, the Test, Assembly and Packaging TechXPOT will feature a technical session, The 3D TSV Revolution, It’s More Than Just Stacking! with speakers addressing 3D integration technologies such as systems integration, system design, TSV processes, materials issues, thin wafer handling and chip stacking, as well as the OSAT perspective.

Then, the Thursday session from 11:00 – 1:20 looks at Survivability Through Collaboration, examining the effectiveness of collaboration between the R&D and manufacturing communities in bring 3D schemes to fruition. Additionally, one presentation (from 2:50-3:10 pm) during the test strategies session on Tuesday talks about Semiconductor Test in the Third Dimension. As test is one of the missing links in the 3D supply chain, it would be great to find some insight here.

Off-site, SUSS MicroTec has just announced they will be hosting a free workshop at the St. Regis, Wed. July 15 from 2-5pm on the topic of Thin Wafer Processing for 3D TSV Applications, in which materials and equipment manufacturers will reveal the latest innovations in thin wafer support systems & backside processing. Also on Wednesday from 1pm-6pm, SEMATECH will be hosting a 3D Metrology Workshop. Attendees should hope to gain information on how new and existing wafer metrology technologies can adapted to measure and improve 3D interconnect processes.

It’s pretty clear I’m going to have to clone myself, at least on Wednesday, to fit all this in! Hope to bump into you there. – F.v.T.

Which comes first, 3D standards or market adoption?

The more I talk to people involved in bringing 3D integration using TSV to market, the more it’s clear that the standards issue is another chicken-and-egg, cart-before-the-horse conundrum. Yes, eventually the industry will need standards, but can they really be set before the processes are established?

While some say that standards need to be in place for market adoption to occur, others say that market adoption will happen, and standards will follow suit to bring the technologies to volume production. What's important to understand here is that 'market adoption' and 'volume production' are not synonomous. The former hopefully leads to the latter, but doesn't have to. A technology can be adopted to the market, but only serve niche applications, correct? In any case, I’m told that first and foremost, there needs to be clear definitions of 3D integration schemes and roadmaps before standardization can even be considered.

Most agree that standards development for certain elements is necessary for 3D integration to reach volume production, they also note that not everything can be standardized. For example, I’ve heard several comparisons with flip chip technologies, noting that although flip chip has been used as a method of interconnect in volume production for some time; there are no standards for the process. Point taken – but then flip chip cannot be compared to the entire 3D integration scheme, but rather only to TSV as a comparable method of interconnect. TSVs exist in many forms, as we discussed at length last week. But it’s only one element. Therefore, it’s not the processes themselves that will be standardized; only the interfaces and interface dimensions, for example the interface of memory to logic in a 3D IC configuration. Additionally, design rules will be needed to address the gaps between front-end and back-end players.

Speculation as to who will set the standards varies from industry organizations like JEDEC, Jisso, ITRS, and SEMI; to the major foundries and IDMS like TSMC, Intel, and IBM. Ultimately, the task will fall to whoever stands to benefit most by investing the necessary resources. Really, it appears that developing standards will be an evolutionary process, and is likely to occur in parallel as 3D integration moves from market adoption to volume production. – F.v.T

Filled vs. conformal vias: the consensus

Dr. Zhang, I think we have reached a verdict.

Bob Patti wrote in to confirm Anonymous Caller’s statement regarding polymer-filled, copper-lined TSVs, and also provided some additional data to support his comments. I’ve taken the liberty of paraphrasing his comments here:

With the caveat that he is not a “big fan” of conformal vias, and merely providing data, Bob stated:

“Certainly filling vias with a polymer makes sense to keep material from being trapped and depending on what processing may need to follow, it may be required. A via-last interposer might be a better solution. However, Dr. Zhang's question was is it possible to metalize both sides without filling, apparently it is, shown here in this ZyCube presentation (see slides 29-30, the CIS pictured is from Oki.)

At Tezzaron, we only use filled tungsten via first (middle) processes. I don't think copper via-first is a good alternative, except for interposers. Tungsten TSVs are, at best, limited to ~20µm depth, so copper is (at least currently) the only alternative for vias needing to go more than ~20µm deep. So interposers really must use copper. The issue with filled copper at high aspect ratios and/or large diameters is the exposure to thermal cycling. An interposer will not be exposed to numerous 300-400°C temperature cycles, as a copper via-first chip would be. So interposers are far more likely to tolerate filled vias.

Most memories that I am familiar with, other than our own, are via-last copper. I think they are also conformal, but I could be wrong. This makes them look like the Oki sensor."

So in general, the consensus is that as long as the via formation occurs after the metallization layers, as in via last for CIS, or certain interposer applications, a conformal via is fine. Otherwise, the via should be filled with something: copper, tungsten, or polymer. Got it. -- F.v.T.

A final (?) word on filling TSVs

Now look what I’ve started. After posting Bob Patti’s solution for performing UBM with conformal TSVs, I got a phone call from a 25 year industry veteran who prefers not to be identified, but who disagreed with Bob’s response. He maintains that when forming TSVs in a via-first approach for the purpose of silicon interposers, they must be either completely filled with copper, or lined with copper and filled with either a polymer material or solder, because if you attempt to put a redistribution layer or UBM layer on without filling them, “all the junk” will fill the via. He also noted that in the case of via-last formation for CMOS image sensor applications, there is no need to completely fill the via. I forgot to ask him if the same applies with DRAM memory stacks, which is Tezzaron’s area of specialty, so I’m thinking we may not have heard the last of this discussion.

Although a purely coincidental happenstance, yesterday’s debate turns out to be the ideal lead-in for my next announcement. Beginning July 6, and running through July 24th I will be moderating the BrightSpots 3D IC Forum, hosted by MCA Public Relations in cooperation with SemiNeedle, which will enable industry professionals to participate in an active discussion exploring the key issues surrounding 3D ICs from design to manufacture. The online round-table format offers a platform for continuous dialogue that extends the life of a traditional panel event and features a panel of industry experts ready to discuss critical issues associated with 3D IC technology initiated by questions from the public. To join the online discussion or log on to monitor progress, visit www.semineedle.com/MCA3DIC. You can also monitor BrightSpots-related activities on Twitter under the hash tag: #MCA3DIC. I’m very excited to be a part of this event, and look forward to covering it on my blog. – F.v.T.

TSV copper fill: is it necessary for UBM?

In response to a recent post about the whether/when it is necessary to completely fill TSVs, or sufficient to line them, I received an inquiry from Dr. Zhang of IME, where he has been researching with TSV formation for 2 ½ years. According to Zhang, he hasn’t been able to build reliable vias without completely filling them (either with all copper or copper liner + polymer or other materials). He cited an illustration from a paper he co-authored for ECTC 2009, titled Package Development of Through Silicon Via (TSV) Interposer Technology for Large Die (21x21mm) Fine-pitch Cu/low-k FCBGA (proceedings pp. 305-312) which demonstrates that it is necessary to completely fill the vias in order to perform front- and back-side metallization/UBM (under bump metallurgy). The example shown here is performed for a TSV interposer application.

Zhang inquired how it is possible to do front-side and back-side metallization/UBM without filling the vias. As I am an industry journalist and not a research scientist, I decided to pose the question to my readership, both to help Dr. Zhang further his research, and also to help create the atmosphere of interactivity I’m hoping to inspire with this blog.

If any of you can provide an answer to this question, please let me know, and I’ll post the response here. – F.v.T

More about UBM for conformal TSVs

In response to the previous post, Bob Patti of Tezzaron Semiconductors weighed in with a solution to performing under bump metallization (UBM) on conformal (lined rather than filled) TSVs. Patti says that Dr. Zhang is correct in stating that you can't put UBM on top of a conformal TSV. However, he suggests solving the issue by placing a pad next to the TSV and putting the UBM there. Thanks for your help, Bob! - F.v.T.

News from IMEC’s technology forum

From the looks of my inbox, it’s been a busy week at IMEC, between the 25th anniversary celebration and technology forum.(Incidentally, Bill Acito of Cadence provided the words behind the IMEC acronym in response to my last post. According to the link he gave me to Wikipedia, IMEC stands for either Interuniversity Microelectronics Centre, or International Medical Equipment Collaborative. I’m guessing the one the IMEC we’re all familiar with is the first.)

Probably the most significant announcement is the passing of the president and CEO batons from Gilbert Declerck, who has held that position for the past 10 years, to Luc Van den hove, who was been with the organization for his entire career in various roles, most recently as Executive V.P. and Chief Operating Officer. Van den hove says he intends to continue building on the foundation established by Declerck during his tenure, and will continue to develop research partnerships to connect technology and industry, expanding activities in application-oriented research.

Also noteworthy for 3D integration followers is the expanded partnership with TSMC. The Taiwanese semiconductor foundry announced plans to expand its R&D efforts, and has decided to base its European R&D efforts at IMEC. That news, combined with the company’s announcement in April that its 300mm fab will be ready to manufacture TSVs by June, leads me to believe that the gears might start turning towards market adoption.

Other announcements from the technology forum were in the area of photovoltaics research with Schott Solar, brain research, and spectrum sensing capabilities for cognitive radios. Details can be found here on IMEC’s website. – F.v.T

What’s your semi lingo IQ?

I’ve long been fascinated with the vernacular of the semiconductor industry, which is riddled with acronyms that can often mean different things whether you’re referring to front-end or back-end applications. Additionally, as 3D technologies have developed, so has a whole new set of terms that are evolving right along with the processes. It certainly makes for interesting discussion, as I found out last week at ECTC 2009 (that's Electronics Component Technology Conference).

For example, SoP can mean small-outline-package or system-on-package depending on who you talk to, and before SiP referred to a system-in-package, it was a single-inline-package (not to be confused with a DiP, or dual-inline-package). And before a system-in-package was called a SiP, it was referred to as a MCM, or multichip module. Confused yet? Jeanne Beacham, of Delphon, and I started joking in the buffet line at the conference. “What’s so great about PoP,” quipped Jeanne Beacham of Delphon. “What about MoM?” I laughed, but then again, it’s entirely possible. PoPs made of multichip packages could be called multichip-on-multichip (MoM). They certainly will be able to do lots more than a PoP (I’ll just leave it at that).

What’s more, we toss around terms like FEOL and BEOL (front-end-of-line and back-end-of-line) and FOUP (front opening unified pod) like everyone knows what we’re talking about. (I actually had to look that one up while writing this. I know what FOUPS are; those orange thingies that hold the wafers before and after processing. I just didn’t know what the letters stood for.)

All kidding aside, settling on a set of terms for 3D processes is actually the first step to standardization, notes Eric Beyne, of IMEC. We were discussing how chip and die are used interchangeably, (specifically in reference to die-to-wafer stacking or chip-to-wafer stacking.) and the confusion it causes for those who distinguish between the die and the chip based on whether it’s bare or packaged. Last year, we were told via first could be further distinguished into via-early (before CMOS) or via-middle (after CMOS but before BEOL). Oh great, there’s another one. (For those about to ask, CMOS stands for complementary metal oxide semiconductor. No wonder we don’t usually write that out.) In any case, Beyne says the ITRS (International Technology Roadmap for Semiconductors) is working to standardize definitions, because classification of technologies is required to define a roadmap.

Incidentally, if someone can tell me what IMEC stands for, the drinks are on me. – F.v.T.

TSVs: just the tip of the 3D ICeberg

At ECTC last week, I counted at least 21 presentations dedicated to TSVs alone, and 13 dedicated to other processes for 3D IC integration. The sheer volume and depth of research required around bringing these technologies to market is sometimes lost on those of us who sit outside the circle of academia and research, and only hear about those that make it to marketability. And although TSVs have become the poster child for 3D IC integration, sometimes we forget that there are other steps of equal importance to achieving these 3D stacks; namely backgrinding, thinning and dicing; temporary bonding and debonding for both wafer-to-wafer (W2W) chip-to-wafer processes (C2W); and chip stacking.

According to IMEC’s Eric Beyne, while many companies are involved in developing materials and equipment for TSV processes (etch, seed layer, fill, etc.) there are only 2 equipment manufacturers (EV Group and SUSS MicroTec) that offer tools for temporary bonding and debonding processes, and only a few materials companies (Brewer Science, 3M, and Dupont) developing temporary bonding materials. Beyne described one temporary bonding material that when heated, allows the device wafer to slide apart from the carrier wafer; and another that vaporizes the material holding them together. Unfortunately, both of these materials involves high temperatures, which, when used in sequential processes to achieve multiple chip stacks, can stress the ultrathin device wafers. Therefore, IMEC is working on a parallel process to overcome address this. One approach is to stack the chips using a sort of stencil to maintain alignment, and then perform the bond step all at once.

Chip stacking is another step still requiring some solutions in C2W processes, where the perfect combination of speed and accuracy is yet to be achieved. S.E.T has developed a high-precision, flexible die bonder that reportedly achieves a throughput of 150pph, earning the company installs at IMEC, SEMATECH and CEA-Leti; but according to Mike Thompson, CTO of Replisaurus, S.E.T’s parent company, that number needs another zero (1500) to make it volume-production-capable. Solving this alignment plus throughput conundrum is the focus of TNO’s Bluebird project with Datacon. As part of the EMC3D consortium, EV Group is also working with Datacon to solve the C2W stacking issue.

What’s not being revealed is likely to be more important than what is being revealed. As was pointed out to me on more than one occasion last week, companies aren’t likely to talk about what they’re working on until it’s a done deal. And they never talk about what they’ve tried that has failed, which could ultimately be as useful for competitors to know about as the successes are. In any case, it appears that there’s still work to do before all the stars align. – F.v.T.

News in 3D: the plot thickens at ECTC

Gossip flies at industry events. But usually as soon as someone tells me something juicy, they follow up with “but you can’t write about that yet.” Do you realize how hard that is? When, WHEN can I tell? Other times, I guess the answer, and can tell I’ve hit the nail on the head by the silent response and look on the interviewee’s face. But still, I’m sworn to secrecy with the promise of being the first to know when the news is ready to go public. I’ve got a few things under my hat at the moment. I’ve been sitting on one scoop for the better part of a year now.

It’s much more fun to be given the inside story and be the first to tell it. For example, I get to be the first to formally announce that Kathy Cook, previously of SUSS MicroTec, has joined Alchimer as business development manager. We talked about recent accomplishments (as in yesterday) for Alchimer, which involved proving thermal reliability of electrografting copper seed on titanium nitrite. According to Frédéric Raynal, product development manager for Alchimer, this is significant because the availability of reliability information has been an obstacle in achieving customer specifications. So the company had a third party perform reliability tests. So far, after 500 thermal cycles, thermal reliability was achieved from -55°C to 125°C. Results of 1000 cycle reliability tests will be available in June.

Additionally, at SEMICON West this year, Alchimer will launch the full AquiVia line , building on last year’s launch of egViaCoat, which replaces the dry PVD process for applying a seed layer on TSVs with electrografting, which is a wet process. The AquiVia “trilogy” completes the wet process, replacing conventional dry process flow for insulation (CVD), barrier (PVD/CVD/ALD), and seed (PVD) layers with proprietary wet-based electrografting, chemical grafting, and electrografting processes, respectively.Remember, you heard it here first. There I feel much better now. – F.v.T.

Live from San Diego, it’s ECTC 2009

When I attend a conference like ECTC, packed with densely detailed technical presentations, I realize just how much work has to happen behind the scenes to bring all these technologies to production. The devil is clearly in the details. In the 3D space alone, there were dozens of papers and posters being presented from across the spectrum of university and research organizations, although proving possible in laboratory settings, many of the processes being discussed will likely never see the light of day in volume production, while others will provide the Eureka moments we’ve all been waiting for. However all of this work is critical to the ultimate mainstreaming of processes, and subsequent development of standards.

As Toshiaki Itabashi of Dupont WLP Solutions, explained to me while leading me through his poster session, Integrated Materials Enabling TSV/3D-TSV, thousands of man hours go into to developing these processes and perfecting the materials. Once the right recipe is achieved, it makes sense for it to become standard going forward.

I had one of those Eureka moments listening to Juergen Leib, research consultant to AAC Microtec, describe a silicon interposer with TSV developed for a space application. For this application, he said the decision was made to merely line a TSV with copper, rather than fill it. Lining it is all that’s required to achieve electrical conductivity, and reduces the potential stress put on the silicon by filling the via with copper. Additonally, the potential for delamination is reduced. “Wait a minute,” I asked. “If it’s not necessary to fill the via, why do it?” Both Leib and Eric Beyne of IMEC provided the answer. It all depends on the application and the diameter of the via. Beyne explained that for vias smaller than 25µm, filling is necessary because lining only can create voids. Another reason to fill is in stacking chips, which requires a microbump on top of each via. In that case, you need to fill to create the bump. But other TSV applications, lining the via is sufficient, and may ultimately create a stronger structure. So there you have it. I learn something new every day. – F.v.T.

Tezzaron’s multi-project wafer program: participant perspective

Tezzaron’s multi-project wafer program: participant perspectivesTo follow up with last week’s report on Tezzaron’s multi=project wafer program (MPW), I asked a few of the participants to share information about their part in the project, and the benefits of working in this paradigm. The first respondent was Donald Chiarulli, Professor of Computer Science and Computer Engineering, University of Pittsburgh.

To be considered for the program, potential participants had to submit project summaries outlining wafer “real estate” specifications, along with justification for their proposed project. In the case of the U. of Pittsburg, Chiarulli requested “a 5mm x 5mm die with DRAM stack attached to implement a hardware test-bench for a single hop, routerless system-level-interconnection network architecture.” The goal is to develop a low-latency high-throughput, system-level interconnect that enables the next-generation systems, which have thousands of processors tightly integrated with large memories.

“In this project, we are rethinking system-level interconnection networks for large scale 3D ICs,” explained Chiarulli. To this end, Chiarulli and his team, Prof. Steven Levitan, and graduate student, Kelli Ireland, were allotted a die stack consisting of two CMOS die and two memory die. According to Chiarulli, to emulate a large-scale network in the area provided, processor cores at each node in the network were replaced with simple controller nodes that emulate read, write, and coherence traffic between L1-caches and set of shared L2 caches. “Our work is based on a partitioned bus, with a fan-in/fan-out architecture that takes advantage of the increased interconnection density and shortened wire lengths that are characteristic of 3D integration,” said Chiarulli. So when you read about how one of the drivers of market adoption for 3D IC using TSVs is repartitioning, this is what’s being talked about; a way to leverage high levels of integration that can only be provided by 3D hybrid chip stacking technology.

Chiarulli considers MPW runs, such as this one, critical to computer architecture research. “Simulation only gets you so far and there is no substitute for validating results with prototype devices. Continued support by industry and government in making this run available for academic research is very important.”

I expect to hear from other participants in this project, so stay tuned… ~F.v.T

Jisso International Council 2009: Defining 3D

Last week, I heard from the North American delegation of the Jisso International Council (JIC), reporting on the recently concluded annual meeting at the Minatec facilities in Grenoble France, which this year was focused on 3D terminology. Collectively, they contributed the following guest post:

The Jisso International Council (JIC) successfully completed its 10th annual meeting at the facilities of Minatec in Grenoble, France, at which the third dimension was a key topic. JIC’s interest in 3D is predicated on their ongoing efforts to harmonize standardization and industry terminology for electronic interconnections. 3D interconnections are blurring the once well-defined and bright lines that separated the various hierarchical elements of the electronics universe. As a result, the council is now looking for ways to help the broader industry communicate more effectively as these nascent technologies begin to take hold and grow.

There were several excellent and informative presentations made by council members in an effort to help identify and resolve some of the many challenges that accompany the development and growth of this new area of high interest to the electronics design and manufacturing community. In the first part of the JIC’s 3D session, Eric Beyne, IMEC (Belgium), Nicolas Sillon, CEA- Léti (France) and Juergen Wolf, Fraunhofer Institute (Germany) provided a comprehensive review of the economical considerations of the various TSV technologies that are increasingly popular.

3D technology, it was concluded, is essentially a collection of stacked chip versions using both “vias-first” and “vias-last” production methods. Related technologies not only allow for the stacking or layering of interconnect routing layers, as has long been the design tradition, but now also allow the stacking of actual active component layers to provide a “More than Moore” total integration solution. This is perhaps the most distinctive feature of 3D integration, as it allows for the realization of electronic systems with a much higher packaging efficiency, measured both in terms of density per unit area and per unit volume.

The second session reviewed TSV-3D applications and production scenarios with presentations by Hirofumi Nakajima, NEC (Japan), Claudius Feger, IBM (USA), Bernd Roemer, IFX (Germany), Caroline Beelen-Hendrikx NXP (Belgium) and Jacques Ferrara, ST Micro (France). Their presentations indicated that application drivers for 3D technologies are numerous and diverse. Among the top drivers were reduced size and form factor, which are obvious ones, but there are others drivers as well.

For example, device bandwidth and clock frequency are basically “flat-lining” in the world of 2D interconnections, and there is a need for more heterogeneous integration including RF, analog, logic, memory and sensors. Another driver is power reduction in an increasingly power hungry world. Other advantages include modularity and the potential of IP re-use to lower time-to-market and cost.

In summary, 3D technology is definitely on the rise both figuratively and literally, but there are many hurdles still to clear and much understanding still required. The technology resides largely in the domain of research but is rapidly moving to production. It seems clearly to be headed to a bright future, but its success will be gated by the quality of the communications that are employed to carry forward and codify the lessons learned.

Just as I'd hoped, it seems as though Françoise in 3D is becoming more than just a blog, but also a forum for the 3D community to contribute information. Keep it coming! -- F.v.T

Walker confirms; SATS Industry is healthy

Yesterday's post resulted in an email from Jim Walker, Research VP, Semiconductor Manufacturing, Gartner Dataquest. I've known Jim for several years, as he served on Advanced Packaging magazine's advisory board, and have often consulted with him on market research for the Semiconductor Assembly and Test Services (SATS) sector. I thought his comments should be shared with my whole readership as more than just a comment to the original post. So with his permission, I've decided to post his email here, in its entirety:

Françoise –

Thanks for writing your blog on the SATS market today. It appears that someone in the press was taking 2 separate recent reports we wrote on the SATS market and combined them into one, resulting in confusion for the readers. One report on the SATS market share for 2008 (which you referenced) dealt with revenue numbers. The other report, by David Christensen, our factory database analyst, discussed manufacturing facilities and the square footage of factory space that has and will be changing over the next year regarding IDM and the SATS companies. I agree with your assessment that the SATS industry is healthy and not in 'dire' straights.

I have received a lot of emails concerning the articles and wondering what was going on with the industry.

Regards,

Jim Walker

So there you have it, straight from the source. Thanks for clarifying that, Jim. -- F.v.T

Is SATS revenue declining or relocating?

What’s that you say? The SATS sector is set for further declines? Really? Or is that yet another negative perspective being expressed by the trade press? Ok, one publication’s headline reporting Gartner’s latest findings grabbed my attention, while I experienced that “oh no here we go again” feeling in the pit of my stomach. Further reading on other industry sites unearthed a more balanced picture. Yes – numbers are down due to the global economy. Nothing earth shattering there. But the solid numbers reported past revenue from 2008 backwards, and anything going forward is purely speculative.

Let’s talk about what’s really happening. Although the SATS sector reported losses last year, they still outpaced the overall semiconductor industry. In fact, several of the OSATS providers – STATS ChipPAC, Unisem, and Powertech all reported growth over 2007. The expected 40% drop in back-end semiconductor manufacturing capacity is reportedly expected at IDMS not the OSATS providers. That number has more to do with IDMS and OEMS adopting an outsource model and shifting the work to packaging houses. As a result, Gartner predicts a 60% capacity increase for the OSATS in the same time frame. In fact, ASE recently reported being awarded a sizeable contract by Intel. One big enough, in fact, that it is likely to boost ASE’s revenues past the expected level. The contract is reportedly due to Intel’s closing of in-house packaging and test facilities.

According to an article I read in Taiwan Economic News, other IDMS such as NXP Semiconductor, Renesas, and Toshiba are expected to follow suit; and other OSATS will benefit. So rather than an overall loss in revenue wouldn’t this be more appropriately termed a shift in revenue? And don’t all parties ultimately benefit as resources are conserved in one place as they are expanded in others? I think they call this restructuring, and at the end of the day, the industry as a whole might just benefit.

So how does this relate to 3D technologies? Clearly, OSATS play an integral part in market adoption of 3D IC integration technologies. I suggest that volume production of 3D WLP and 3D IC stacking using TSVs could be the missing variable to tip the scales in the favor of OSATS who invest in those production capabilities. When numbers are reported next year, will the companies who took on the challenge be the ones reporting growth? That’s what I want to know. – F.v.T.

Can cost-sharing accelerate 3D IC commercialization?

I’ve been talking a lot about the collaborative efforts in the form of open and closed consortia and joint development agreements that seem to be carrying 3D IC integration forward to market adoption. Another approach is a multi-project wafer program, in which participants cost-share to build multiple device prototypes on a single wafer. The intention is to bring the resulting prototypes to commercialization more quickly and at a lower cost to each member than if they were developed individually.

One such program is Tezzaron Semiconductor’s multi-project wafer program, first reported a few months back on Phil Garrou’s 3D blog, Perspectives from the Leading Edge. According to Garrou’s post, the project would allow up to 10 participants to buy a share of wafer real estate for the purpose of developing prototype 3D IC logic devices. The intention was for each participant to design its own 3D logic device, which would be built in Tezzaron’s proprietary FaStack process. Each logic device would then be integrated with a Tezzaron 3D DRAM to create a hybrid memory/logic 3D-IC. Hmm, I thought, cool approach. I need to find out more.

Unfortunately, the project went dark,(it was initially sponsored by DARPA, and mum’s the word when government agencies are involved.) However, the embargo has lifted, and last week I had a lengthy chat with Gretchen Patti, of Tezzaron Semiconductor. While she couldn’t reveal details of specific devices being tested in 3D by participants, she did say they primarily fell into one of two categories; processors and sensors. For the non-techies among us (like me), Patti offered a simple description of the process.

Figure 1 illustrates how two levels of logic are being built on one wafer. Suppose that the two red squares belong to a participant prototyping a processor, the two yellow squares belong to a participant prototyping a sensor technology, etc. The processor is designed with two layers of circuitry. One layer is built in the red square on Side 1, the other on Side 2. Similarly, the sensor is designed with two layers of circuitry that are built in the two yellow squares. Now we build a whole bunch of identical wafers. Each wafer is stacked face-to-face on an identical wafer. In this way, the sensor dies line up, and the processors line up. When the wafers are bonded, the sensor’s two layers of circuitry become a single circuit, and so do the processor layers. The final project wafer consists of different logic devices, each designed by a different participant.

Next, logic devices are then stacked on a Tezzaron 3D DRAM wafer, which was also created as a wafer-to-wafer stack using tungsten-filled TSV interconnects. The final output is various logic-on-memory devices, assembled in a die-to-wafer process using TSV interconnects (Figure 2). One of the benefits of multiple projects being designed using the same memory wafer is that the logic is then designed to interface with a standard memory, so that although the memory wafer is not customized to each device, it attaches as if it was.

According to Patti, the project has taken on a life of its own, and has grown beyond the original intention to include 19 participants from both the public and private sector, including several universities (U. of Pittsburgh, U. of Michigan, and Johns Hopkins, to name a few.)

“We couldn’t believe the response,” she said. “We didn’t even publicize it.” They ended up with 30 applicants, more than twice as many as they expected. There’s no doubt about it, it’s an attractive alternative for companies who can’t swing their own processing costs, but want to test their product to see if it works in 3D. “People are ready,” notes Patti. I’ll say. Look for more on this as I talk to some of the university participants about specific projects. – F.v.T.

3D innovation: prevention or cure?

In his editorial yesterday, Steve DeCollibus, managing editor of Semiconductor Packaging News, offered some food for thought about the concept of the semiconductor industry innovating its way out of this downturn. To illustrate his point, he tracks the evolution of the integrated circuit itself – a technical innovation that took 80 years to complete.The point he makes is this: true innovation takes time, dedication, collaboration, and full participation of everyone from academia and R&D, across the entire supply chain. It’s not something that can be done, as he puts it “on demand.” I couldn’t agree more.

Innovation shouldn’t be seen as the antidote, or cure to the current economic pandemic. Rather, ongoing treatment seems to be much a much more potent measure against the disease. For example, 3D integration technologies have been the innovation flavor-of-the-month since long before the current economic disaster hit. Is it by pure coincidence that those companies who continued to push forward and invest in these technologies are the ones who were more resistant to the downturn virus? I’m talking about start-up companies like Alchimer, Replisaurus and Imbera, who managed to raise venture capital to develop their technologies; and established equipment manufacturers like SUSS MicroTec, Surface Technology Systems, and EV Group, who have all recently reported installs in both research and production settings. According to Steve Dwyer, director of sales, North America, EVG, in the past 3 weeks, EVG has received 6 tool orders for TSV processes in North America alone, 4 of which are headed for production lines, while the other two will go to research settings.

Although it may seem that the “Pollyannas” of the industry (myself included) have been dishing out the “innovate out of the downturn” mantra as a way to bolster morale, it’s not without basis. However, perhaps a more accurate explanation is that during a downturn, there is less time spent manufacturing and shipping product, and more time to focus on innovation. The companies who took advantage of that time seemed to be hit less badly by the downturn, and those who were already innovating and continued on that path were the most resistant to the effects of the downturn. After all as, Benjamin Franklin once said, an ounce of prevention is worth a pound of cure. – F.v.T

Semi Standards – a 3D conundrum?

I got into an interesting conversation recently with Steve Dwyer, of EV Group, about the puzzling situation 3D IC integration is posing with regard to existing Semi Standards, and those yet to be established as 3D IC integration processes are developed.

Take, for example, the standard for wafer handling. Dwyer explained that the current standard calls for a process wafer to be returned to the same slot in the FOUP where it came from. But with temporary bonding for thin wafer handling, the input comes from two separate FOUPs, and the output is the two wafers bonded together, so one FOUP winds up with an empty slot, thereby breaking the standard for handling wafers. Clearly, the standard was set based on single wafer processes, and didn’t consider future possibilities of multiple wafers being combined into a single processed wafer.

Additionally, when it comes to establishing standards for 3D IC integration processes, all the different processes being developed — via-first, via-early, and via last; front side approaches vs. back-side approaches; wafer-to-wafer, chip-to-wafer and chip-to-substrate — will need to be considered.

So what’s the hurry? Is the establishment of standards for 3D IC integration critical for market adoption to take place? Would it be better to hold off until the processes shake out and we see what sticks? Consider also that if multiple approaches are adopted, then standards will need to be set to accommodate different options. “Until the industry works out what it wants to do, we need the flexibility,” notes Dwyer.

I posed this question to Sitaram Arkalgud of SEMATECH’s 3D interconnect program, and Rich Brilla, of the College of Nanoscale Science and Engineering (CNSE) at the University at Albany. Brilla noted that in addition to standards focused on equipment and processes, design ground rules are also needed. For example, knowing where alignment marks should be for wafer to wafer and chip to wafer processes is critical. Part of the work being done by SEMATECH at CSNE will help to establish these standards.

“It takes ages for standards to come together. It’s a voyage of discovery,” notes Arkalgud, adding that this work-in-progress approach to standards is still better than having nothing at all. “3D can revolutionize the industry, but needs standards in order to make it happen, otherwise it will delay the adoption of technology,” he said; a sweeping statement perhaps, but his point is well taken. Without standards to bring the technology to high volume, it runs the risk of just being a niche market. – F.v.T.

Another step forward for EDA Tools

I have to admit, I’ve always had difficulty trying to wrap my head around software, especially design tools. So I’ve come to have a deep respect for those individuals charged with the task of designing the design tools themselves. Not only do they need to be able to visualize the end result, they have to work backwards to anticipate the steps required to get there, and then figure out a way to archive that knowledge for later use. In essence, before a design tool can be designed, the methodology of the steps to achieve this must be established. Then, EDA tool designers create a tool based on these established methodologies to be able to automate the design processes for manufacturing.

Current 2D tools have no notion of a 3D hierarchy and thus no way to build IP libraries for 3D. To design 3D ICs, designers had to resort to tricking 2D tools by renaming design layers or creating multiple copies of standard cell libraries. This “design-by-hand” works fine for 2.5D structures like CMOS image sensors and homogenous 3D DRAM memory stacks, but as Lisa McIlrath, of R³Logic, pointed out during the panel discussion at DATE 2009, logic/memory stacks and true heterogeneous integration will need fully functioning 3D design tools.

Understanding the ramifications of this is what makes R³Logic's latest achievement of that much more noteworthy. The company was recently awarded a patent for “methods and systems for computer aided design of 3D integrated circuits”. According to a company statement, the patented invention comprises both the method of defining a 3D technology file that can incorporate one or more 2D wafer technologies corresponding to different tiers in a 3D stack, and that of defining a 3D hierarchical structure for functional blocks within a 3D system. Managing multiple design libraries while properly handling IP blocks that reside on more than one tier is crucial to 3D system design, notes R3Logic, whether at the circuit layout or at the system architecture level.

Achieving this milestone brings th 3D design pioneer another step closer to proving the industry with the tools they’re seeking. I offer my congratulations and look forward to hearing more about it. – F.v.T

June Events in 3D

As May rolls right into June, so do the 3D events; or should I say events in which 3D topics are addressed. Indeed, it seems as if 3D is permeating just about everything. From looking at the programs, it’s clear that organizers are struggling with categorizing presentations to fit under one categorical umbrella. Oftentimes, while there are dedicated tracks, there’s overflow into others. Another thing to note are those presenters who are “doing the circuit” so-to-speak. If you’re fortunate enough to be attending more than one of these events, you can maximize your conference time by being aware of possible re-runs.

June 2-4 IMEC Technology Forum 2009
Celebrating it’s 25th year, IMEC has re-christened the Annual Research Review Meeting (ARRM) to IMEC Technology Forum (ITF). While the event will cover the gamut of IMEC’s work, specific to 3D technologies will be Eric Beyne’s presentation on heterogeneous integration,and how it will require advances in 3D technologies including: through-Si-via connections, ultra-thin die thinning, high density interconnect die stacking and die embedding technologies. Following Beyne’s presentation, Ingrid De Wolf will address metrology, test and reliability challenges brought on not by 3D chip stacking, also for co-integration of MEMS on top of CMOS and other heterogenous configurations.

June 14-17, The Confab, Las Vegas, NV
Of particular interest to those of us following 3D IC integration issues, will be the session at Confab on Tuesday, June 16, 2:15 PM - 3:45PM titled Economic Implications of Test. In light of test complexities brought on by 3D IC integration such as redundancy, KGD issues, built-in self-test and repair, etc., speakers will address the economic scalability of the test roadmap over the next 3 to 5 years, by examining test drivers, test flow simplification, and “Test Lite” philosophy.

June 15-18, EMPC 2009, Rimini, Italy
European Microelectronics and Packaging Conference (EMPC), combines the efforts of IMAPS Europe; IEEE Components, Packaging, and Manufacturing Technology Society (CPMT); and iNEMI into one biannual event. This year’s event is jam-packed with 3D. Of specific interest to me will be Rao Tummala’s tutorial and subsequent keynote, Beyond 3D ICs to 3D Systems. Additionally, each member of the EMC^3D consortium will give a presentation as part of its tutorial session on Monday, June 15. On Thursday, two of the advanced packaging sessions will be devoted to 3D packaging, in addition to 3D related presentations scattered throughout the program as they apply to other categories such as Hannes Kostner’s presentation in the flip chip track, Impact of 3D Packaging Technologies on Flip Chip Equipment; Fraunhofer’s contribution: 3-D Packaging Concept for Cost-effective Packaging of MEMS and ASIC on Wafer-level; to name only a few. Trust me, you won’t run out of things to do at this one. Plus who can resist Rimini in June?

June 28-July2 2009 Lithography Workshop, Coeur d’Alene, Idaho
Historically, this even focused on leading-edge lithography. This year, presentations will include advances in 3D architectures and packaging. A panel discussion, moderated by Dan Hutcheson, debating the pros and cons of advanced lithography vs. advanced packaging and 3-D structures (taller vs. smaller) will be held on Wednesday evening, July 1, 2009.

That wraps it up for June, with the Big Kahuna – SEMICON West, right around the corner. No doubt that event will get a post or two all of its own. Stay tuned. – F.v.T

My Big Fat 3D Obsession

In one of my all-time favorite movies, My Big Fat Greek Wedding, family patriarch, Kosta Portukalo is obsessed with his own culture, “Give me a word, any word, and I will show you how the root of that word is Greek.” I’m starting to feel that way about 3D technologies. Give me a new technology, any technology, and I will show you how it qualifies as a 3D configuration, either at the chip, package or system level.

For example, Yesterday, I interviewed the team at Texas Instruments (Roland Pang, Larry Nye and Matt Stovall) responsible for launching the company’s PicoStar ultra-thin chip package. While this initial device — an ESD/EMI filter that involves a single die, and achieves a low profile by interconnecting to the board via Cu-Ni-Pd pillar bump — is an achievement in and of itself as an ultra-thin package, it doesn’t really make the cut as a 3D configuration. However, the minute I heard “embedded in the PCB to reclaim board space” my 3D antennae perked up. While the first roll-out of package is intended to be board mounted using standard pick-and-place assembly processes, the second generation will be an embedded device with copper pillar bump interconnects, and is assembled a build-up process currently being developed with board manufacturers-who-could-not-be-named. (Imbera or Ibiden perhaps? Just a guess on my part – but I’ll be keeping my ears open). Embedding the device uses the Z-direction to free up board space (reportedly 90% over the standard ESD/EMI leadframe package) for either more functionality or overall reduction in end product.

Then, when Pang and Nye explained how it could be mounted on a "daughter" package to create a more robust ESD/EMI solution than the daughter package alone, I thought, hmmm.... so it can be assembled in a PoP configuration, once again using the Z-direction to reduce form-factor, thereby qualifying it, by my definition anyhow, as a 3D solution at both the package and board levels – so, there you go! – F.v.T

May Events in 3D

I wish I could be everywhere at once, because there are so many events involving 3D coming up well worth attending. Unfortunately short of cloning myself, which I don’t think the world is ready for, there’s no way for me to cover everything. So instead, I’ve come up with an alternative plan that I hope will also serve to make this blog more interactive, and encourage an exchange of ideas and information in the 3D space. I’ll list the events here and point out the 3D highlights. If you think you’ll be attending, and have time to contribute a brief review or even just a few comments from whatever event/sessions you attend, please drop me a line.

May 13, Through-Silicon Vias (TSVs): Design and Reliability, Santa Clara, CA
This dinner/presentation, co-sponsored by IEEE Santa Clara Valley CPMT Society Chapter, with Electron Devices Chapter, Reliability Chapter, and Circuits and Systems Chapter features Sergey Savastiouk of ALLVIA, who will address the physical design and reliability issues associated with copper through-silicon vias that have not been fully resolved. I suspect that Savastiouk, considered to be one of the pioneers in TSV and founder of the first TSV foundry, can certainly provide a first-hand perspective of what is yet to be overcome before TSV reaches full market adoption. Harvey Miller of IEEE will guest blog this event. I’m looking forward to reading his review.

May 20 – 22, SEMICON Singapore 2009
Known as the Asian epicentre for test, assembly and packaging, this SEMI-sponsored event has always been the one to focus in the back-end. A review of the symposium line-up turned up two 3D focused presentations; New Packaging Solutions for Wireless: Wafer Level Package 3D Evolution, presented by Xavier Baraton, of ST Microelectronics Pte Ltd; and Approaches and Strategies for TSV, presented by Vish Srinivasan of Applied Materials.

May 27-29, ECTC 2009 – San Diego, CA
In addition to the obvious 3D focused sessions, such as 3D IC integration, TSV, Interconnects for 3D IC integration, and TSV characterization, 3D focused presentations cross over into many of ECTC’s sessions. To name a few, as part of the advanced flip chip packaging session, representatives of STATS ChipPAC will present a paper titled “Three-tier PoP Configuration Utilizing Flip Chip Fan-In PoP Bottom Package”; and as part of the MEMS MEMS, Sensors, and Embedded Packaging Technologies session, representatives of Infineon will present a paper about 3D image sensors using 3D interposers. Even though I plan on attending and covering as much as I can myself, I’d certainly welcome guest blogger contributions for this event.

May 29, 2009 Design Technologies for 3D Integration – CEA-Leti, Grenoble, France
As an extension of their R&D partnership, CEA-Leti and Ecole Polytechnique Fédérale de Lausanne (EPFL), have launched a monthly seminar series for students and professionals to discuss technical issues facing micro- and nanotechnology researchers. This seminar, led by Dr. Vasileios Pavlidis, will take place at Leti, in Grenoble France.

That’s a lot happening for one little month. Since May jumps right into June, and events are happening early, I’ll post June events later this week. – F.v.T

3D from all angles at DATE 2009 3D workshop

As I was unable to attend Design Automation Test in Europe (DATE 2009) myself, but felt the information being shared there would be useful to my readers, I asked fellow 3D enthusiast, Yann Guillou, new technology marketing, St Ericsson, if he would write a guest post for “Françoise in 3D”. He graciously agreed, and what follows is his coverage of the event. -- F.v.T

Overview
Nice, in the French Riviera, hosted a hot event on 3D TSV integration in late April. Indeed, one of the Friday workshops of DATE 2009 was dedicated to 3D integration and brought together experts from design, architecture, process, test, and packaging. More than 70 industrial and academic attendees from Europe, Asia and the US attended. In these difficult economic times, it is a proof of the quality of the papers and speakers. Luckily, I had the opportunity to co-chair the event with organizer Erik Jan Marinissen from IMEC and his colleague Geert Van der Plas.

Keynotes
The workshop started with two talks delivered by invited speakers, followed up by 6 papers selected out of 35 submissions, more than 20 posters. A panel discussion with 3D experts concluded this intense day.

Sitaram Arkalgud from Sematech delivered a keynote address on the promises of TSV, and addressed the main technological challenges. He went through all the process steps and options to achieve 3D structures with TSV. Very clear in his explanations, his presentation enabled the test, design, architecture community of DATE to have a global overview of the TSV technology. He showed some cost simulation done by Sematech and stressed that the applications will drive most of the choices. He concluded by sharing results of a survey done by Sematech listing the main challenges of 3D TSV seen by the companies. And surprisingly for some people, the TSV process did not appear to be the most challenging item. 3D design tools and methodologies, thermal management, supply chain definition or test strategy were among the top ranked. Technology was not. He insisted on the need for a roadmap, and again, a roadmap based on the applications. As of today, most of the TSV roadmaps are technology driven, bottom-up roadmaps. He would recommend a top-down assessment from the system driver. That would help in building coherent 3D R&D and getting the critical mass. He concluded by stating TSV was not a single technology element but part of a whole of domains and competencies.

The second invited speaker, Riko Radojcic from Qualcomm, gave some flavors on Qualcomm CAD strategy for 3D TSV. He insisted on what he calls “Pathfinding,” “TechTuning,” and “Design Authoring.” He underlined the thermo-mechanical challenges related to 3D TSV and the new paradigm coming. Difficulties will come from the multi-scale thermo-mechanical analysis that will be required with 3D structures: mm scale at packaging level, µm at chip level, nm scale at transistor level. He added a 2.5D design environment should be enough at the beginning for stacks of dies up to 2. Then, a real 3D environment will be required.

Presentations
Interests of TSV for different applications were presented by both STMicroelectronics and Toshiba for multimedia and multi-core processors. Endicott Interconnect showed some R&D work on advanced substrates with vertical vias (not TSV in that case!), eventual sufficient solutions for particular applications. Georgia Tech presented test solutions for 3D, whereas IMEC presented some results based on the cost model tool they internally developed.

Panel Discussion
Pol Marchal (IMEC) moderated the final panel discussion. Showing 3D TSV samples done at IMEC, he provocatively asked the panelists: “Look, it is possible to make it; we did stack of die with TSV.” He asked them: “Why not tape out products next year?”

Nicolas SIllon (CEA-LETI) gave an overview of LETI latest developments. He announced it will soon be possible to manufacture product with low-density TSV. LETI will be ready for it. Regarding high-density TSV, he added he was wondering if there were today some applications requiring thousands of TSV with diameter of a few microns only.

Paul Siblerud presented EMC3D latest developments and underlined the most critical process steps to make TSVs. He concluded by saying some challenges were existing but none were seen as a show stopper.

Pascal Urard (STMicroelectronics) presented the first products on the market from STMicroelectronics with TSV, the image sensors. He answered the moderator’s question by saying, yes, we can manufacture products with TSV. They are not 3D at IC level today, but they could be in future.

Geert Van der Plas (IMEC) highlighted that the analog and RF community should be more involved in 3D TSV as many improvements could come from this technology.

Krishnendu Chakrabarty (Duke University) gave some insight on test and explained the nice concept of “pretty good die” for 3D.

Finally, Lisa McIlrath (R3Logic) pointed out the fact that CIS or a stack of DRAM with TSV can be designed "by hand" whereas logic/memory or true heterogeneous cannot.

The panel session finished the day on an optimistic note. Let’s solve all these challenges now!

An Electronic Workshop Digest is available for download at the workshop’s web site
Contact Yann Guillou at Yann.Guillou@stericsson.com

The post-fab process debate for 3D ICs: foundry or OSATS

Inquiring minds want to know: who is going step forward and claim ownership of post-fab processes for 3D IC stacking using through-silicon vias (TSVs)? This has been a topic of debate for some time, with no real solution, although plenty of reasons why one or the other is the way to go, depending on who you talk to. Here's my understanding of the situation.

First of all, there’s a hodge-podge of process flows being tossed around. Some are more suited to a fab environment, and others are more suited to an OSATS environment. Additionally, some approaches are suited to specific applications. For example, CMOS image sensors, the first TSV application in production, uses a via-last approach that requires no adaptation to front-end technologies. However, memory stacks are targeting via-first due to a lower cost-of-ownership.

To grasp it all, it’s important to understand the basic concepts – creating the vias themselves, and stacking the die. The EMC^3D Consortium has developed two proprietary process flows, iTSV and pTSV, both currently based on a die-to-wafer stacking process rather than wafer-to-wafer. iTSV is a via-first approach, in which vias less than 10 microns are formed after CMOS process, but before BEOL processes. Alternatively pTSV is a via-last approach, with vias formed before bonding, but uses the packaging infrastructure.

According to Tom Gregorich, VP of packaging at Qualcomm, there are two process flow options for creating TSV through-silicon stacks (TSV TSS) using a via-first approach. In the die-to-wafer flow, stacking happens during post-fab processing, and the diced die stack is treated as a single die in the assembly processes. In a die-to-substrate flow, the diced top and bottom bumped die arrive at the assembly house independent of each other, and are stacked directly on the substrate medium at assembly house.

In either of these flows, the processes that happen at the foundry end at via formation, and the flows are identical up to the micro-bumping step. Post-fab processes of thinning, dicing, and stacking can occur either at the foundry, the OSAT or a third, yet to be established location. Gregorich says the difference is that die-to-wafer requires post-fab process to be co-located with the OSATS, due to the fragile and expensive die stack, but with die-to -substrate can be independent of each other. “ TSV/TSS requires a significant expansion of and investment in post fab processing operations,” he notes.

So according to Gregorich, the million dollar question is who will make the investment in post-fab processes, the foundries or the OSATS? Thus far, he says the base of technology is already in the OSATS, and Amkor is investing in the TSS processes. But will foundries who invest in TSV processes also invest in the post-fab processes? TSMC just announced it will ready its 300mm facility for TSV processes by June. Will they take the leap and extend that to include post-fab processes for D2W stacks?

If everyone is right, then it doesn’t seem to be a case of either or, but rather, an application-specific issue. As we often see when it comes to this industry, the solutions are never straight forward. In this case, the savviest of fabs and OSATS will see opportunity in the investment, and both options will be available. Meanwhile, those involved in developing processes, equipment and materials are covering all the bases to ensure what they’re developing can suit all the available scenario: via-first or last; W2W or C2W, foundry or OSAT. That’s my take on the situation. I’m curious to know what others think will happen. ( Don’t be shy – that’s what the comment function is meant to be used for.) – F.v.T.

Following the 3D innovation path to profitability

In last week’s email update, I talked about the pendulum starting to swing back the other way, albeit ever so slightly. It’s little things, such as SEMI’s book-to-bill rising from a frightening .48 to a less ominous .61; to bigger things, like TSMC announcing they will invest in R&D despite a hiring freeze in other sectors. As part of it's roadmap to innovate its way out of the slump, the company claims it will have its 300mm fab ready to manufacture TSVs by June. This is exciting news for equipment and material suppliers who have committed to investing in TSV processes.

Whether or not you're a proponent of TSV, it’s clear that companies who are investing in those technologies are faring better these than those who are hacking away at the bottom line to weather the storm. It seems to be working for SUSS MicroTec and EV Group, who have both invested in developing tool sets for wafer bonding, lithography, and mask aligning for the 3D IC integration market. Last week, SUSS announced an order from Nemotek Technologie for multiple lithography systems to be used for manufacturing the company’s CMOS images sensors (CIS). As CIS was the first application to adopt TSV processes in volume production, this win helps establish SUSS as an equipment provider for CIS.

On the heels of that news, came EV Group’s announcement that they will increase production capacity due to “strong order intake” driven by R&D investment in the 3D IC and nanoimprint lithography markets. EV Group strategically established itself in academia, shrewdly anticipating that while capex spending would fall off in the public sector, universities and research institutes would be investing in 3D IC integration to be ready for the rebound.

In his recent SemiSpice blog post, Tom Morrow recounts the different approaches taken by both Kelloggs and Post to survive the Great Depression. Reading it, I thought of Lam Research and Applied Materials (AMAT), equipment vendors who both offer etch tools for 3D IC applications. See if you can guess who is the Post and who is Kelloggs in this scenario. In December 2008, AMAT made headlines with its launch of the Silvia etch tool, then joining EMC^3D and most recently entering into a joint development agreement with Disco to develop wafer thinning processes for TSVs. The only news I’ve seen about Lam in the same time frame is a layoff of 600 employees in November, and another 375 in March. Both layoffs were part of a plan to reduce Lam’s cost structure. In December, Applied announced a cash dividend, while in April, Lam announced a quarterly loss.

While cost cutting may help the bottom line in the short term, it’s my experience that in the long run, innovation and investment goes a lot further to improve a company’s image and ultimately its bottom line, not to mention establish company moral and loyalty. Kudos to the companies and organizations that choose not only to invest and innovate, but also publicize accomplishments. It gives us all something to strive for. -- F.v.T.

(incidentally if you’re not getting the update and would like to, subscribe here.)

Lisa McIlrath, R3 Logic: design tools for 3D IC are on the way

Mea culpa. I may have jumped to conclusions in yesterday’s post. Although it appears to those developing 3D IC integration processes that the design community hasn’t been heeding the call for the much needed design tools, after talking with Lisa McIlrath of R3 Logic, I realized there’s a lot more to it than that. In fact, the message has been heard, but these things are more convoluted than we think. In fact, it's a bit of a cart-before-the-horse situation. How can design tools be developed until the process technologies, characterization, and paramaters have been determined, and prototypes tested? For that matter, each customer is likely to establish its own design rules.

Consider that 3D IC integration is still a very new field, and that everyone is very much in what McIlrath called “pathfinding mode”; exploring different designs before having the parameters figured out. She said that there’s lots of advance work being done to discover different customer needs. Design tools needed now for CMOS image sensors and soon for stacked memory may not necessarily turn out to be the same ones needed down the road for heterogeneous integration. Unfortunately, it’s still not clear what the winning applications will be.

For large companies, there's not much incentive to invest in development until the picture is clearer and the market is big enough. However the buzz is that Cadence has been some internal development, and and Synopsis and Mentor are sending some of their people to Friday’s 3D Integration Workshop at DATE 2009, in Nice, France. Clearly, the interest is growing.

McIlrath said that although it might be risky and difficult for small companies to set a course on a tool that may not be adopted, it’s also easier for them to be agile as the market shifts and changes. For example, R3 Logic discovered a need by the research community for a layout editor, so they partnered with MicroMagic to develop one. (Tezzaron Semiconductors, pioneers in manufacturing stacked memory with TSVs uses the tool, and has endorsed it.) This week at DATE 2009, McIlrath says R3 Logic will be showcasing a 3D floorplanning tool scheduled for install this summer. Additionally, last month, the company announced a collaboration with ST-Microelectronics and CEA-LETI to develop a full 3D design flow.

McIlrath says that although it’s regrettable that there aren’t more tools out there and available, she doesn’t agree that the lack of design solutions, or test for that matter, is a blocking factor in TSV adoption. “3D integration is going to go ahead with or without any particular player,” she said. “The design tools are coming. Our goal is to find the most appropriate tools to suit the needs of the users.” – F.v.T

DATE 2009 Addresses Design for 3D Integration

It looks as though the call is finally being heard. Those deeply involved in 3D IC Integration using through silicon vias (TSV) as a method of interconnect have been banging these particular drums and sending up smoke signals to the design and test communities for quite some time now with the same message: WE NEED DESIGN SOLUTIONS and WE NEED METHODS FOR TEST.

During the 3D Panel held last month at IMAPS Device Packaging Symposium, panelists and attendees alike speculated about the why’s and wherefores of the logjam for both; but no one could really come up with a concrete answer. While several smaller EDA vendors were acknowledged for having developed tools for 3D IC design (Javelin Design Automation, MicroMagic, and R3 Logic), the question of when “the big guys” (Mentor and Cadence) would jump on board. The collective assumption is that until TSV is closer to market adoption, there’s no real need for the larger design houses to jump into the ring. Test for TSV is still very much an enigma.

Therefore, it was with delight that I reviewed the agenda for Friday’s workshop at DATE 2009, 3D Integration – Technology, Architecture, Design, Automation and Test. Workshop organizers, Yann Gillou, of ST Ericcson, and Erik Jan Marinissen and Geert Van der Plas, both from IMEC; have assembled a line-up for attendees from the design and test communities designed to educate attendees about the critical need for solutions, and to spark interaction between researchers, practitioners, and others interested in 3D IC Integration.

Session 1, moderated by Lisa McIlrath of R3 Logic, kicks off with a keyote addressby Sitaram Arkalgud, of SEMATECH, titled The Promise of Through-Silicon Vias, followed by invited speaker, Riko Radojcic from Qualcomm, who will outline requirements for the design-for-3D environment. The talk will focus on the design environment and EDA tools necessary for what Qualcomm identifies as the ‘Stage 1’ class of products, consisting of a functionally partitioned two-die stack. He will identify three classes of methodologies and associated EDA technologies.

The rest of the day addresses the gamut of issues surrounding design and test, ranging from power integrity issues and bandwidth optimization, to SOC test architecture, test strategies for 3D IC, and much more. In addition to live presentations and 22 poster sessions, the day will conclude with a panel discussion, The Future of 3D Integration From All Angles, moderated by Peter Ramm, of the Fraunhofer Institute. Panelists include Roger Carpenter, Javelin Design Automation; Krishnendu Chakrabarty, Duke University; Paul Siblerud, Semitool; Nicolas Sillon; CEA-LETI; Pascal Urard, ST Microelectronics; and Geert Van der Plas, IMEC.

They may not have the answers yet, but at least they’re getting the message. It’s a start. -- F.v.T