Can cost-sharing accelerate 3D IC commercialization?

I’ve been talking a lot about the collaborative efforts in the form of open and closed consortia and joint development agreements that seem to be carrying 3D IC integration forward to market adoption. Another approach is a multi-project wafer program, in which participants cost-share to build multiple device prototypes on a single wafer. The intention is to bring the resulting prototypes to commercialization more quickly and at a lower cost to each member than if they were developed individually.

One such program is Tezzaron Semiconductor’s multi-project wafer program, first reported a few months back on Phil Garrou’s 3D blog, Perspectives from the Leading Edge. According to Garrou’s post, the project would allow up to 10 participants to buy a share of wafer real estate for the purpose of developing prototype 3D IC logic devices. The intention was for each participant to design its own 3D logic device, which would be built in Tezzaron’s proprietary FaStack process. Each logic device would then be integrated with a Tezzaron 3D DRAM to create a hybrid memory/logic 3D-IC. Hmm, I thought, cool approach. I need to find out more.

Unfortunately, the project went dark,(it was initially sponsored by DARPA, and mum’s the word when government agencies are involved.) However, the embargo has lifted, and last week I had a lengthy chat with Gretchen Patti, of Tezzaron Semiconductor. While she couldn’t reveal details of specific devices being tested in 3D by participants, she did say they primarily fell into one of two categories; processors and sensors. For the non-techies among us (like me), Patti offered a simple description of the process.

Figure 1 illustrates how two levels of logic are being built on one wafer. Suppose that the two red squares belong to a participant prototyping a processor, the two yellow squares belong to a participant prototyping a sensor technology, etc. The processor is designed with two layers of circuitry. One layer is built in the red square on Side 1, the other on Side 2. Similarly, the sensor is designed with two layers of circuitry that are built in the two yellow squares. Now we build a whole bunch of identical wafers. Each wafer is stacked face-to-face on an identical wafer. In this way, the sensor dies line up, and the processors line up. When the wafers are bonded, the sensor’s two layers of circuitry become a single circuit, and so do the processor layers. The final project wafer consists of different logic devices, each designed by a different participant.

Next, logic devices are then stacked on a Tezzaron 3D DRAM wafer, which was also created as a wafer-to-wafer stack using tungsten-filled TSV interconnects. The final output is various logic-on-memory devices, assembled in a die-to-wafer process using TSV interconnects (Figure 2). One of the benefits of multiple projects being designed using the same memory wafer is that the logic is then designed to interface with a standard memory, so that although the memory wafer is not customized to each device, it attaches as if it was.

According to Patti, the project has taken on a life of its own, and has grown beyond the original intention to include 19 participants from both the public and private sector, including several universities (U. of Pittsburgh, U. of Michigan, and Johns Hopkins, to name a few.)

“We couldn’t believe the response,” she said. “We didn’t even publicize it.” They ended up with 30 applicants, more than twice as many as they expected. There’s no doubt about it, it’s an attractive alternative for companies who can’t swing their own processing costs, but want to test their product to see if it works in 3D. “People are ready,” notes Patti. I’ll say. Look for more on this as I talk to some of the university participants about specific projects. – F.v.T.