Bluebird: A project in 3D Equipment Development

I consider myself to be fairly savvy when it comes to knowing who the players are in 3D IC technology research, so when I first saw the news article in EDN reporting that TNO, an Eindhoven-based scientific research company, had approached BESI/Datacon to develop a high-end pick-and place tool for die-to-wafer (D2W) stacking, I felt a bit chagrined; I had never heard of TNO. So I set out to find out as much as I could. It occurred to me that maybe there were others like me out there who had been in the dark.

Bluebird Basics
It turns out that TNO has a fairly broad reach in scientific research, with one arm extending into the development of high-end equipment for specific markets. One of the projects falling under this division is the Bluebird Project, led by R.M.W. (Roger) Gortzen. Its aim is to develop integrated equipment for the purpose of manufacturing 3D IC devices cost effectively and at high volume.

According to the website page about the program, this equipment is intended for 3D stacking using TSVs, rather than wire bonding, as the method of interconnect. Gortzen talks about an integrated system with processed wafers prior to via construction as input, and outputs stacked die. Steps to be eliminated include optical inspection, wafer feeders, transportation between separate machines, and some materials. The long-term goal of this project (target completion 2016) is to achieve stacked-die 300 mm wafers at $100/wafer.

To this end, Gortzen has worked with IMEC to identify the current bottlenecks in the process. The first phase will focus on standardization for the project, thin wafer and die handling, pick and place for die-to-wafer (D2W), bonding, and particle inspection.

Enter BESI/Datacon
Gortzen has clearly been listening to other players in the industry. Citing presentations given at IMAPS 2008, SEMICON West, and by members of EMC3D, here’s what he heard; there isn’t a tool on the market that is appropriate to stack 3D packages. He proposes that a new platform design with more placement-per-second and higher-accuracy aligment at low cost is required. This brings us to the recent news about the collaboration with BESI/Datacon.

Datacon brings experience in advanced D2W technologies, as they have been collaborating on these processes for quite some time with EV Group. That work resulted in a toolset consisting of high-volume flip chip bonding equipment for a pre-bond process, at which point fully assembled wafers were transferred to a die-to-wafer bonder for permanent bond.

Hannes Kostner, of BESI, was happy to answer some questions regarding BESI/Datacon’s involvement in Bluebird. “The project between BESI/Datacon and TNO is one part of Bluebird,” he explained.”This subproject is called BlueHawk and the target is to develop a high accuracy flip chip bonder with a placement accuracy of the already mentioned 2.5µm at 3sigma.”

I asked why a project targeting TSV stacking would be based on a flip chip platform. He explained that Datacon’s 8800 FC Quantum is a perfect platform to start a high accuracy development because it already achieves a performance mix of throughput and accuracy in the order of 10µm at 3sigma at approx. 8000 uph. Additionally, he said it’s not to a drawback to start from a flip-chip only machine, because it’s really just a question of presenting dies on the dicing tape for D2W production. “A flip chip machine is potentially faster since the handling of dies is split into two parallel processes; ejection and flipping and measurement and placement,” he said. With this process, Kostner said the TSVs are formed before die placement so the diebonder can handle the current TSV approach.

A prototype of the TNO/BESI/Datacon tool is scheduled for introduction by the end of this year, with commercial launch sometime in 2010. The companies say they are confident that this tool will be the production tool of the future for D2W processes in the emerging market of 3D stacking.

So there you have it. Now you know what I know. And now that the Bluebird project is on my radar, I’ll be sure to stay on top of it.–F.v.T.

Talking the 3D Talk

I was happy to share the 3D stage as a contributing editor in this week’s issue of AP Semi-monthly. In fact, I found Yann Gillou’s guide to 3D vernacular: 3D Lingo-Getting it Straight really helpful for sorting out the differences between 3D configurations at the package and IC levels, and TSV. Gillou and I met last October at SEMICON Europa, where he explained to me how TSV is often identified as a 3D configuration by itself, when it reality, it is what he calls a “techno brick” used to achieve “real” 3D ICs. It was great to read the final article inspired by this conversation. It’s definitely worth the read.

I was also glad to see 3D ASSM’s presentation at Pan Pacific Symoposium in Hawaii get some ink from George Riley in The Riley Report. Only a month and a half away from the official kick-off, over 45 organizations from the industry, academia, and government have rfeportedly put forth efforts through the planning stages. Riley’s column offers a comprehensive look at the challenges to be overcome if the development of this system-on-wafer technology is to succeed. Just in case you missed these articles in the original eNewsletter, I’ve taken the liberty of linking to them from here. - F.v.T.

EDA Tool Addresses 3D Design Limitations

One by one, it looks like to-do items are being checked off the list of TSV adoption limitations for 3D ICs, and it seems that collaborative efforts are making the most progress in achieving desired consequences. For example, we’ve been hearing the cry for design tools for quite some time, and yesterday Javelin Design Automation, in cooperation with IMEC and Qualcomm, announced a breakthrough with its Pathfinder tool for design exploration and optimization of 3D stacked ICs (3D SIC).

According to a joint statement, The team developed a detailed 3D flow to determine accurate performance/power/cost estimates for a 3D stack. The flow was then validated by using it in a smart phone application. The results demonstrated how using TSVs as the method of interconnect allows for a decrease in power, thereby allowing for an increase of bus-width between microprocessor and memory.

Pol Marchal, principal scientist of IMEC who worked on the project, explained some of the ramifications of this work to me. “The PathFinding tool brings 3D technology one step closer to adoptation as it helps to assess the cost/benefits of 3D technology in the early phases of design.” he said. IDMs hesitate to adopt 3D, he explained, because they don’t understand system benefits. Additionally, he said if they do have ideas, they have no way to determine how their system-level decisions might complicate physical designs. By creating a prototype with this tool, the system design team can obtain valuable insights in the power/performance/cost trade-offs for various 3D integration scenarios. One example of comparing these trade-offs was with IMEC’s studies in 3D WLP vs. 3D SIC.

Additionally, integration and packaging teams can benefit from reviewing the prototypes to address and perhaps eliminate manufacturing challenges 3D stacks pose down the line. For example, Marchal explained, can the envisioned 3D stack be packaged? Can the dissipated power be removed from the stack? Is the stack mechanically reliable? Relying on a prototype rather than a spreadsheet allows for practical and focused discussion, which in turn allows for easier evaluation of alternative integration schemes. “As 3D system-level decisions have such impact on final cost, we believe that physical design prototyping will become an essential step in the 3D design flow,” said Marchal, adding that in addition to the path finding tool, obvious follow-ons will include design authoring and verification tools for 3D place and route, layout, layout versus schematic check / design rule check, extraction, etc.

What’s most interesting to me in this latest achievement, is the demonstration once again of the power of collaboration to bring ideas closer to fruition. In cases like this, everybody wins. Javelin gets to be the first out of the gate with a marketable tool that’s been validated by two reputable organizations. IMEC has access to a tool that could very well catapult forward further research in 3D integration. Qualcomm gets to reap the benefits as an early adopter of 3D technologies in their products. I’d say that’s a pretty good start to the week. – F.v.T.