News in 3D: the plot thickens at ECTC

Gossip flies at industry events. But usually as soon as someone tells me something juicy, they follow up with “but you can’t write about that yet.” Do you realize how hard that is? When, WHEN can I tell? Other times, I guess the answer, and can tell I’ve hit the nail on the head by the silent response and look on the interviewee’s face. But still, I’m sworn to secrecy with the promise of being the first to know when the news is ready to go public. I’ve got a few things under my hat at the moment. I’ve been sitting on one scoop for the better part of a year now.

It’s much more fun to be given the inside story and be the first to tell it. For example, I get to be the first to formally announce that Kathy Cook, previously of SUSS MicroTec, has joined Alchimer as business development manager. We talked about recent accomplishments (as in yesterday) for Alchimer, which involved proving thermal reliability of electrografting copper seed on titanium nitrite. According to Frédéric Raynal, product development manager for Alchimer, this is significant because the availability of reliability information has been an obstacle in achieving customer specifications. So the company had a third party perform reliability tests. So far, after 500 thermal cycles, thermal reliability was achieved from -55°C to 125°C. Results of 1000 cycle reliability tests will be available in June.

Additionally, at SEMICON West this year, Alchimer will launch the full AquiVia line , building on last year’s launch of egViaCoat, which replaces the dry PVD process for applying a seed layer on TSVs with electrografting, which is a wet process. The AquiVia “trilogy” completes the wet process, replacing conventional dry process flow for insulation (CVD), barrier (PVD/CVD/ALD), and seed (PVD) layers with proprietary wet-based electrografting, chemical grafting, and electrografting processes, respectively.Remember, you heard it here first. There I feel much better now. – F.v.T.

Live from San Diego, it’s ECTC 2009

When I attend a conference like ECTC, packed with densely detailed technical presentations, I realize just how much work has to happen behind the scenes to bring all these technologies to production. The devil is clearly in the details. In the 3D space alone, there were dozens of papers and posters being presented from across the spectrum of university and research organizations, although proving possible in laboratory settings, many of the processes being discussed will likely never see the light of day in volume production, while others will provide the Eureka moments we’ve all been waiting for. However all of this work is critical to the ultimate mainstreaming of processes, and subsequent development of standards.

As Toshiaki Itabashi of Dupont WLP Solutions, explained to me while leading me through his poster session, Integrated Materials Enabling TSV/3D-TSV, thousands of man hours go into to developing these processes and perfecting the materials. Once the right recipe is achieved, it makes sense for it to become standard going forward.

I had one of those Eureka moments listening to Juergen Leib, research consultant to AAC Microtec, describe a silicon interposer with TSV developed for a space application. For this application, he said the decision was made to merely line a TSV with copper, rather than fill it. Lining it is all that’s required to achieve electrical conductivity, and reduces the potential stress put on the silicon by filling the via with copper. Additonally, the potential for delamination is reduced. “Wait a minute,” I asked. “If it’s not necessary to fill the via, why do it?” Both Leib and Eric Beyne of IMEC provided the answer. It all depends on the application and the diameter of the via. Beyne explained that for vias smaller than 25µm, filling is necessary because lining only can create voids. Another reason to fill is in stacking chips, which requires a microbump on top of each via. In that case, you need to fill to create the bump. But other TSV applications, lining the via is sufficient, and may ultimately create a stronger structure. So there you have it. I learn something new every day. – F.v.T.

Tezzaron’s multi-project wafer program: participant perspective

Tezzaron’s multi-project wafer program: participant perspectivesTo follow up with last week’s report on Tezzaron’s multi=project wafer program (MPW), I asked a few of the participants to share information about their part in the project, and the benefits of working in this paradigm. The first respondent was Donald Chiarulli, Professor of Computer Science and Computer Engineering, University of Pittsburgh.

To be considered for the program, potential participants had to submit project summaries outlining wafer “real estate” specifications, along with justification for their proposed project. In the case of the U. of Pittsburg, Chiarulli requested “a 5mm x 5mm die with DRAM stack attached to implement a hardware test-bench for a single hop, routerless system-level-interconnection network architecture.” The goal is to develop a low-latency high-throughput, system-level interconnect that enables the next-generation systems, which have thousands of processors tightly integrated with large memories.

“In this project, we are rethinking system-level interconnection networks for large scale 3D ICs,” explained Chiarulli. To this end, Chiarulli and his team, Prof. Steven Levitan, and graduate student, Kelli Ireland, were allotted a die stack consisting of two CMOS die and two memory die. According to Chiarulli, to emulate a large-scale network in the area provided, processor cores at each node in the network were replaced with simple controller nodes that emulate read, write, and coherence traffic between L1-caches and set of shared L2 caches. “Our work is based on a partitioned bus, with a fan-in/fan-out architecture that takes advantage of the increased interconnection density and shortened wire lengths that are characteristic of 3D integration,” said Chiarulli. So when you read about how one of the drivers of market adoption for 3D IC using TSVs is repartitioning, this is what’s being talked about; a way to leverage high levels of integration that can only be provided by 3D hybrid chip stacking technology.

Chiarulli considers MPW runs, such as this one, critical to computer architecture research. “Simulation only gets you so far and there is no substitute for validating results with prototype devices. Continued support by industry and government in making this run available for academic research is very important.”

I expect to hear from other participants in this project, so stay tuned… ~F.v.T

Jisso International Council 2009: Defining 3D

Last week, I heard from the North American delegation of the Jisso International Council (JIC), reporting on the recently concluded annual meeting at the Minatec facilities in Grenoble France, which this year was focused on 3D terminology. Collectively, they contributed the following guest post:

The Jisso International Council (JIC) successfully completed its 10th annual meeting at the facilities of Minatec in Grenoble, France, at which the third dimension was a key topic. JIC’s interest in 3D is predicated on their ongoing efforts to harmonize standardization and industry terminology for electronic interconnections. 3D interconnections are blurring the once well-defined and bright lines that separated the various hierarchical elements of the electronics universe. As a result, the council is now looking for ways to help the broader industry communicate more effectively as these nascent technologies begin to take hold and grow.

There were several excellent and informative presentations made by council members in an effort to help identify and resolve some of the many challenges that accompany the development and growth of this new area of high interest to the electronics design and manufacturing community. In the first part of the JIC’s 3D session, Eric Beyne, IMEC (Belgium), Nicolas Sillon, CEA- Léti (France) and Juergen Wolf, Fraunhofer Institute (Germany) provided a comprehensive review of the economical considerations of the various TSV technologies that are increasingly popular.

3D technology, it was concluded, is essentially a collection of stacked chip versions using both “vias-first” and “vias-last” production methods. Related technologies not only allow for the stacking or layering of interconnect routing layers, as has long been the design tradition, but now also allow the stacking of actual active component layers to provide a “More than Moore” total integration solution. This is perhaps the most distinctive feature of 3D integration, as it allows for the realization of electronic systems with a much higher packaging efficiency, measured both in terms of density per unit area and per unit volume.

The second session reviewed TSV-3D applications and production scenarios with presentations by Hirofumi Nakajima, NEC (Japan), Claudius Feger, IBM (USA), Bernd Roemer, IFX (Germany), Caroline Beelen-Hendrikx NXP (Belgium) and Jacques Ferrara, ST Micro (France). Their presentations indicated that application drivers for 3D technologies are numerous and diverse. Among the top drivers were reduced size and form factor, which are obvious ones, but there are others drivers as well.

For example, device bandwidth and clock frequency are basically “flat-lining” in the world of 2D interconnections, and there is a need for more heterogeneous integration including RF, analog, logic, memory and sensors. Another driver is power reduction in an increasingly power hungry world. Other advantages include modularity and the potential of IP re-use to lower time-to-market and cost.

In summary, 3D technology is definitely on the rise both figuratively and literally, but there are many hurdles still to clear and much understanding still required. The technology resides largely in the domain of research but is rapidly moving to production. It seems clearly to be headed to a bright future, but its success will be gated by the quality of the communications that are employed to carry forward and codify the lessons learned.

Just as I'd hoped, it seems as though Françoise in 3D is becoming more than just a blog, but also a forum for the 3D community to contribute information. Keep it coming! -- F.v.T