June Events in 3D

As May rolls right into June, so do the 3D events; or should I say events in which 3D topics are addressed. Indeed, it seems as if 3D is permeating just about everything. From looking at the programs, it’s clear that organizers are struggling with categorizing presentations to fit under one categorical umbrella. Oftentimes, while there are dedicated tracks, there’s overflow into others. Another thing to note are those presenters who are “doing the circuit” so-to-speak. If you’re fortunate enough to be attending more than one of these events, you can maximize your conference time by being aware of possible re-runs.

June 2-4 IMEC Technology Forum 2009
Celebrating it’s 25th year, IMEC has re-christened the Annual Research Review Meeting (ARRM) to IMEC Technology Forum (ITF). While the event will cover the gamut of IMEC’s work, specific to 3D technologies will be Eric Beyne’s presentation on heterogeneous integration,and how it will require advances in 3D technologies including: through-Si-via connections, ultra-thin die thinning, high density interconnect die stacking and die embedding technologies. Following Beyne’s presentation, Ingrid De Wolf will address metrology, test and reliability challenges brought on not by 3D chip stacking, also for co-integration of MEMS on top of CMOS and other heterogenous configurations.

June 14-17, The Confab, Las Vegas, NV
Of particular interest to those of us following 3D IC integration issues, will be the session at Confab on Tuesday, June 16, 2:15 PM - 3:45PM titled Economic Implications of Test. In light of test complexities brought on by 3D IC integration such as redundancy, KGD issues, built-in self-test and repair, etc., speakers will address the economic scalability of the test roadmap over the next 3 to 5 years, by examining test drivers, test flow simplification, and “Test Lite” philosophy.

June 15-18, EMPC 2009, Rimini, Italy
European Microelectronics and Packaging Conference (EMPC), combines the efforts of IMAPS Europe; IEEE Components, Packaging, and Manufacturing Technology Society (CPMT); and iNEMI into one biannual event. This year’s event is jam-packed with 3D. Of specific interest to me will be Rao Tummala’s tutorial and subsequent keynote, Beyond 3D ICs to 3D Systems. Additionally, each member of the EMC^3D consortium will give a presentation as part of its tutorial session on Monday, June 15. On Thursday, two of the advanced packaging sessions will be devoted to 3D packaging, in addition to 3D related presentations scattered throughout the program as they apply to other categories such as Hannes Kostner’s presentation in the flip chip track, Impact of 3D Packaging Technologies on Flip Chip Equipment; Fraunhofer’s contribution: 3-D Packaging Concept for Cost-effective Packaging of MEMS and ASIC on Wafer-level; to name only a few. Trust me, you won’t run out of things to do at this one. Plus who can resist Rimini in June?

June 28-July2 2009 Lithography Workshop, Coeur d’Alene, Idaho
Historically, this even focused on leading-edge lithography. This year, presentations will include advances in 3D architectures and packaging. A panel discussion, moderated by Dan Hutcheson, debating the pros and cons of advanced lithography vs. advanced packaging and 3-D structures (taller vs. smaller) will be held on Wednesday evening, July 1, 2009.

That wraps it up for June, with the Big Kahuna – SEMICON West, right around the corner. No doubt that event will get a post or two all of its own. Stay tuned. – F.v.T

My Big Fat 3D Obsession

In one of my all-time favorite movies, My Big Fat Greek Wedding, family patriarch, Kosta Portukalo is obsessed with his own culture, “Give me a word, any word, and I will show you how the root of that word is Greek.” I’m starting to feel that way about 3D technologies. Give me a new technology, any technology, and I will show you how it qualifies as a 3D configuration, either at the chip, package or system level.

For example, Yesterday, I interviewed the team at Texas Instruments (Roland Pang, Larry Nye and Matt Stovall) responsible for launching the company’s PicoStar ultra-thin chip package. While this initial device — an ESD/EMI filter that involves a single die, and achieves a low profile by interconnecting to the board via Cu-Ni-Pd pillar bump — is an achievement in and of itself as an ultra-thin package, it doesn’t really make the cut as a 3D configuration. However, the minute I heard “embedded in the PCB to reclaim board space” my 3D antennae perked up. While the first roll-out of package is intended to be board mounted using standard pick-and-place assembly processes, the second generation will be an embedded device with copper pillar bump interconnects, and is assembled a build-up process currently being developed with board manufacturers-who-could-not-be-named. (Imbera or Ibiden perhaps? Just a guess on my part – but I’ll be keeping my ears open). Embedding the device uses the Z-direction to free up board space (reportedly 90% over the standard ESD/EMI leadframe package) for either more functionality or overall reduction in end product.

Then, when Pang and Nye explained how it could be mounted on a "daughter" package to create a more robust ESD/EMI solution than the daughter package alone, I thought, hmmm.... so it can be assembled in a PoP configuration, once again using the Z-direction to reduce form-factor, thereby qualifying it, by my definition anyhow, as a 3D solution at both the package and board levels – so, there you go! – F.v.T

May Events in 3D

I wish I could be everywhere at once, because there are so many events involving 3D coming up well worth attending. Unfortunately short of cloning myself, which I don’t think the world is ready for, there’s no way for me to cover everything. So instead, I’ve come up with an alternative plan that I hope will also serve to make this blog more interactive, and encourage an exchange of ideas and information in the 3D space. I’ll list the events here and point out the 3D highlights. If you think you’ll be attending, and have time to contribute a brief review or even just a few comments from whatever event/sessions you attend, please drop me a line.

May 13, Through-Silicon Vias (TSVs): Design and Reliability, Santa Clara, CA
This dinner/presentation, co-sponsored by IEEE Santa Clara Valley CPMT Society Chapter, with Electron Devices Chapter, Reliability Chapter, and Circuits and Systems Chapter features Sergey Savastiouk of ALLVIA, who will address the physical design and reliability issues associated with copper through-silicon vias that have not been fully resolved. I suspect that Savastiouk, considered to be one of the pioneers in TSV and founder of the first TSV foundry, can certainly provide a first-hand perspective of what is yet to be overcome before TSV reaches full market adoption. Harvey Miller of IEEE will guest blog this event. I’m looking forward to reading his review.

May 20 – 22, SEMICON Singapore 2009
Known as the Asian epicentre for test, assembly and packaging, this SEMI-sponsored event has always been the one to focus in the back-end. A review of the symposium line-up turned up two 3D focused presentations; New Packaging Solutions for Wireless: Wafer Level Package 3D Evolution, presented by Xavier Baraton, of ST Microelectronics Pte Ltd; and Approaches and Strategies for TSV, presented by Vish Srinivasan of Applied Materials.

May 27-29, ECTC 2009 – San Diego, CA
In addition to the obvious 3D focused sessions, such as 3D IC integration, TSV, Interconnects for 3D IC integration, and TSV characterization, 3D focused presentations cross over into many of ECTC’s sessions. To name a few, as part of the advanced flip chip packaging session, representatives of STATS ChipPAC will present a paper titled “Three-tier PoP Configuration Utilizing Flip Chip Fan-In PoP Bottom Package”; and as part of the MEMS MEMS, Sensors, and Embedded Packaging Technologies session, representatives of Infineon will present a paper about 3D image sensors using 3D interposers. Even though I plan on attending and covering as much as I can myself, I’d certainly welcome guest blogger contributions for this event.

May 29, 2009 Design Technologies for 3D Integration – CEA-Leti, Grenoble, France
As an extension of their R&D partnership, CEA-Leti and Ecole Polytechnique Fédérale de Lausanne (EPFL), have launched a monthly seminar series for students and professionals to discuss technical issues facing micro- and nanotechnology researchers. This seminar, led by Dr. Vasileios Pavlidis, will take place at Leti, in Grenoble France.

That’s a lot happening for one little month. Since May jumps right into June, and events are happening early, I’ll post June events later this week. – F.v.T

3D from all angles at DATE 2009 3D workshop

As I was unable to attend Design Automation Test in Europe (DATE 2009) myself, but felt the information being shared there would be useful to my readers, I asked fellow 3D enthusiast, Yann Guillou, new technology marketing, St Ericsson, if he would write a guest post for “Françoise in 3D”. He graciously agreed, and what follows is his coverage of the event. -- F.v.T

Overview
Nice, in the French Riviera, hosted a hot event on 3D TSV integration in late April. Indeed, one of the Friday workshops of DATE 2009 was dedicated to 3D integration and brought together experts from design, architecture, process, test, and packaging. More than 70 industrial and academic attendees from Europe, Asia and the US attended. In these difficult economic times, it is a proof of the quality of the papers and speakers. Luckily, I had the opportunity to co-chair the event with organizer Erik Jan Marinissen from IMEC and his colleague Geert Van der Plas.

Keynotes
The workshop started with two talks delivered by invited speakers, followed up by 6 papers selected out of 35 submissions, more than 20 posters. A panel discussion with 3D experts concluded this intense day.

Sitaram Arkalgud from Sematech delivered a keynote address on the promises of TSV, and addressed the main technological challenges. He went through all the process steps and options to achieve 3D structures with TSV. Very clear in his explanations, his presentation enabled the test, design, architecture community of DATE to have a global overview of the TSV technology. He showed some cost simulation done by Sematech and stressed that the applications will drive most of the choices. He concluded by sharing results of a survey done by Sematech listing the main challenges of 3D TSV seen by the companies. And surprisingly for some people, the TSV process did not appear to be the most challenging item. 3D design tools and methodologies, thermal management, supply chain definition or test strategy were among the top ranked. Technology was not. He insisted on the need for a roadmap, and again, a roadmap based on the applications. As of today, most of the TSV roadmaps are technology driven, bottom-up roadmaps. He would recommend a top-down assessment from the system driver. That would help in building coherent 3D R&D and getting the critical mass. He concluded by stating TSV was not a single technology element but part of a whole of domains and competencies.

The second invited speaker, Riko Radojcic from Qualcomm, gave some flavors on Qualcomm CAD strategy for 3D TSV. He insisted on what he calls “Pathfinding,” “TechTuning,” and “Design Authoring.” He underlined the thermo-mechanical challenges related to 3D TSV and the new paradigm coming. Difficulties will come from the multi-scale thermo-mechanical analysis that will be required with 3D structures: mm scale at packaging level, µm at chip level, nm scale at transistor level. He added a 2.5D design environment should be enough at the beginning for stacks of dies up to 2. Then, a real 3D environment will be required.

Presentations
Interests of TSV for different applications were presented by both STMicroelectronics and Toshiba for multimedia and multi-core processors. Endicott Interconnect showed some R&D work on advanced substrates with vertical vias (not TSV in that case!), eventual sufficient solutions for particular applications. Georgia Tech presented test solutions for 3D, whereas IMEC presented some results based on the cost model tool they internally developed.

Panel Discussion
Pol Marchal (IMEC) moderated the final panel discussion. Showing 3D TSV samples done at IMEC, he provocatively asked the panelists: “Look, it is possible to make it; we did stack of die with TSV.” He asked them: “Why not tape out products next year?”

Nicolas SIllon (CEA-LETI) gave an overview of LETI latest developments. He announced it will soon be possible to manufacture product with low-density TSV. LETI will be ready for it. Regarding high-density TSV, he added he was wondering if there were today some applications requiring thousands of TSV with diameter of a few microns only.

Paul Siblerud presented EMC3D latest developments and underlined the most critical process steps to make TSVs. He concluded by saying some challenges were existing but none were seen as a show stopper.

Pascal Urard (STMicroelectronics) presented the first products on the market from STMicroelectronics with TSV, the image sensors. He answered the moderator’s question by saying, yes, we can manufacture products with TSV. They are not 3D at IC level today, but they could be in future.

Geert Van der Plas (IMEC) highlighted that the analog and RF community should be more involved in 3D TSV as many improvements could come from this technology.

Krishnendu Chakrabarty (Duke University) gave some insight on test and explained the nice concept of “pretty good die” for 3D.

Finally, Lisa McIlrath (R3Logic) pointed out the fact that CIS or a stack of DRAM with TSV can be designed "by hand" whereas logic/memory or true heterogeneous cannot.

The panel session finished the day on an optimistic note. Let’s solve all these challenges now!

An Electronic Workshop Digest is available for download at the workshop’s web site
Contact Yann Guillou at Yann.Guillou@stericsson.com