EVG’s partnership with Léti adds a third dimension

As the old saying goes, things usually happen in threes… and in this case 3D. Three years ago, EV Group (EVG) teamed up with Brewer Science, Inc. (BSI) to develop temporary wafer bonding and debonding processes using EVG tools and BSI's materials. Just a few weeks ago, CEA Léti and BSI announced a joint development program (JDP) for temporary wafer bonding and debonding processes to achieve 3D IC integration using TSVs. Last week, EV Group made a similar announcement regarding a JDP with Leti. Just as I suspected, this move completes a 3-way collaboration for accelerating 3D IC integration. I spoke with Nicolas Sillon, head of the laboratory for advanced packaging and 3D integration at Leti; and Stefan Pargfrieder, EVG's business development manager, to get some more details on the arrangement.

According to Sillon, the program with EVG is complementary to what Leti is already working on with BSI. “We’re mixing three competencies: EVG tools, BSI science, and Leti integration schemes,” he said. Pargfrieder concurred, adding that EVG's previous work with BSI developing temporary bonding and debonding processes on their tools proved the best performance using BSI materials. “To have Léti as an industrial R&D partner allows us to make this a mature qualified technology for a broader range of customers.” he added.

In particular, Sillon said that developing 300mm 3D integration wafer processes is the main goal of the program with EVG. From EVG’s perspective, Pargfrieder says the goal is to establish EVG's technology in the market, and learn from partners about tool performance at the early stages of development to better serve the customer. Therefore, the ability to accomplish this using Léti’s research facilities is a benefit.

As all three entities – Léti, BSI, and EVG – are members of the EMC^3D Consortium, I was curious if this work also tied into that organization. According to both Sillon and Pargfrieder, information will be shared only in as much as can be made public. Sillon says the JDP with both EVG and BSI allows Leti to go deeper into development than they can with EMC^3D . Pargfrieder added that some of the information might be useful to EMC^3D, while some must remain confidential for customer projects.

To learn more about this triad’s work, be sure to catch their presentation on at ECTC 2009, which takes place May 27-29 in San Diego, CA. The topic discussed will be Leti’s via-last application on thin wafers using BSI’s science on EVG’s tool. It looks like the power of 3 is catching on in more ways than one. – F.v.T.

"Francoise in 3D" resurfaces in Mesa, AZ

For the past two weeks, I’ve been slightly preoccupied with relocating from Massachusetts to Mesa, AZ. For much of that time, due to the drive across country and then subsequent delay in installing internet access at my new abode, I was disconnected from the internet and industry activities; needless to say, it’s a slightly unsettling feeling for an industry commentator. Today, FINALLY, I’m up and running once more, and catching up on news. It’s not surprising that while I’ve been on hiatus, organizations and companies devoted to developing 3D technologies have continued to make headlines. Let’s start out by recapping some of the highlights:

Just before I hit the road, Harvey Miller of IEEE contacted me about an upcoming event co-sponsored by IEEE Santa Clara Valley CPMT Society Chapter, and Electron Devices Chapter and Circuits and Systems Chapter titled “Through-Silicon Vias (TSVs): Design and Reliability" Sergey Savastiouk, ALLVIA, Inc. being held May 13, 2009 at the Biltmore Hotel in Santa Clara, CA. Savastiouk is a pioneer in TSV, and is responsible for coining the term itself. His expertise, therefore, encompasses the lifespan of this still emerging technology. With that deep a legacy, it should be iteresting to hear what he has to say about the design and reliability issues that have been identified as critical to market adoption.

Despite the state of the semiconductor industry as a whole, there continues to be optimistic news of growth coming out of the R&D sector, especially with regards to developments in 3D technologies. IMEC announced a 2,800m² addition to its research facilities, to expand its research on, among other things, biomedical electronics. IMEC’s most recent 3D contribution in this area is the ultra-thin chip package. EV Group sold a photoresist developer,the EVG101D, to the University of Tokyo, continuing their success in the academic realm.

Collaboration continues to be the name of the game these days, with more announcements almost daily, such as Applied Materials and DISCO joining forces to jump on the wafer thinning bandwagon for TSV processes. Additionally, EVG and CEA Leti have entered into a joint development program involving EVG’s 300mm temporary bonding and debonding technologies. I’m curious to find out more about the connection between this and Leti’s JDP with Brewer Science. Look for more on the topic later this week.

Are the big design tool houses starting to pay more attention to design for 3D ICs? Phil Garrou’s coverage of an IEEE Components Packaging and Manufacturing Technology (CPMT) workshop in Austin, Texas alludes to Cadence’s involvement in that area. What I’m curious to find out is whether they’re referring to design for stacks interconnnected with wire bond or flip chip, or if they’ve addressed design for TSV integration yet.

So many questions yet to be answered! Count on me to find some answers. – F.v.T.