The Other 3Ds: Occam Process

The brainchild of Joe Fjeldstad, Verdant Electronics, Occam Process got a lot of ink in the press when it was first introduced in 2007. I should know. I recruited several articles from Fjelstad myself for publication in Advanced Packaging Magazine. During an advisory board luncheon at SEMICON West, Fjelstad sidelined me to tell me about the 3D assembly process, which involves a reverse-order interconnect process implemented using existing materials and equipment, resulting a solder-free assembly that is said to achieve such high reliability that Fjelstad jokes about it passing a “throw test” rather than a “drop test.”

Since the initial media frenzy that occurred as all the electronics assembly and packaging publications scrambled to be the “first” or the most “in depth” or even the “most controversial” sources of coverage, Occam has faded from the press limelight. However lack of coverage doesn’t necessarily mean lack of progress, and recent correspondence I received from Harvey Miller, of IEEE, brought Occam duly back on my 3D radar. He shared an article he wrote for PCBOO7, which thoroughly explains what Occam is and what it isn’t, and why Miller endorses Occam as having “the potential to transform electronic manufacturing and restore the competitive position of U.S. and North America as creators of real value.”

I caught up with Fjelstad yesterday. He told me that concepts are beginning to evolve, and pointed out several particularly active areas of interest. “Nacent projects are underway with the Navy,” he said. “They are beginning to develop their own assembly processes based on Occam.” The second area of “burgeoning interest” is in LED lighting. Lead-free materials are an issue with lighting assemblies, because the temperatures are too high, so solder assemblies are running into problems. The solder-free aspect of the Occam prcess makes it a perfect technology for lighting. Interest is also heating up in the automotive industry.

In semiconductor packaging, the Occam Process allows for an innovative 3D stacked package configuration Fjelstad refers to as package-under-package (PuP). “There is possibility to take existing packages and affix one beneath the other creating a PuP and presenting them for assembly using standard SMT processing.” He explained. The module examples shown here include ability to provide metal jackets for shielding and thermal relief.

If the amount of interest can be measured in requests for presentations and keynote addresses, then things are looking good for the future of Occam. ”I gave a presentation yesterday to a room full of top-level technologists from top-tier companies and got a good deal of head nodding during my talk,” noted Fjelstad. “It has wings of its own.” Here’s to a successful flight. – F.v.T.

3D EDA Tools – Coming out of the Woodwork

That didn’t take long. A post about one EDA tool introduction inspired a comment about a 3D layout editor that’s been on the market for 2 years. A mention of said comment in Tuesday’s email update and an email to the individual who posted the comment brought immediate response. This is the beauty of blogging; it results in an almost instantaneous sharing of information and inspires collaboration.

According to Mark Mangum, sales manager for EDA tools and chip design tools at Micro Magic, Inc, the company’s layout editor, MAX 3D, handles the physical design of the chip, and is particularly suited to TSV design. He explained that its ability to manage separate wafer levels with individual tech files is more effective than relying on a "super tech file" to handle the whole design. With this approach, each wafer level maintains its own tech file throughout the design process.There is an additional tech file for the interconnect. In addition, the tool’s speed and capacity is ideal for handling the size and complexity of TSV designs. A slower editor tends to decrease performance drastically.

Three important elements of good EDA tools are programmability, customizability, and compatibility with other tools in the toolbox. Mangum assured me that MAX 3D was developed with these considerations in mind. “Integration is a key selling point for our customers, so we've made an effort to make our tools work with others.” he said, adding that the tool was developed for “open architecture”, with ASCII data files and open source scripting language. OpenAccess support was added for design data files due to customer demand, and is continually updated. To handle Pcell design data, a Pcell interpreter from IPL was added to allows users to read their Pcell data. "MAX-3D has real time design rule checking (DRC), but because many customers use Mentor Calibre for signoff DRC, a direct interface to Calibre was added. We also support industry standard file formats such as GDSII, LEF, DEF, etc. so MAX-3D users won't have to worry about "vendor lock-in" of file formats - for design data, cells, or generators,” he said.

Mangum told me MAX-3D is being used by several universities, including MIT, Lincoln, Cornell, North Carolina State, Penn State. Six companies have also incorporated it into their processes, mainly for developing test chips.

Are there other 3D tools in the works at Micro Magic? Mangum says yes, but is hush-hush about it. "We are working on some packaging-related development with a customer, but no word on when we'll be discussing it," he said. Simulation and verification are big blind spots in the industry right now, he added, but rumor has it, Mentor has something in the works on this.

I know one of Micro Magic’s customers is happy with the performance of the company's tools. An unsolicited endorsement appeared in my inbox shortly after I mentioned the product in my email. Gretchen Patti, technical communications specialist for Tezzaron Semiconductor, stated simply, yet enthusiastically. “About Micro Magic: Their tools are real! We use them.” That’s pretty much all I needed to know. – F.v.T.

The Skinny on 1st Lighten the Load Inc.

First of all – I LOVE the name of this company. For that reason alone, I was intrigued enough to find out more about it, and where it fits in the 3D space. Remember, 3D integration is not only about stacking chips and devices vertically to fit more functionality into less space, it’s about utilizing what ever space is available in the z-direction – which can mean embedding passives and actives into substrate materials, or using conductive inks to get the most out of device real estate. In the case of 1st Lighten the Load, we’re talking about a disruptive technology using printed electronics fabrication to reportedly eliminate the need for 95% of passive components. With this fabrication technology, passive components no longer have a structure of their own, but rather are integrated into an electronics assembly ¼ the thickness of a PCB.

Dave Kelly, CTO of 1st Lighten the Load, Inc. responded to my query for more information on his company’s technology with the following main points:

Passive parts are now printed ink, eliminating their body and allowing them to be incorporated into lower assembly layers.

The metal traces are metal not conductive ink, with low resistance and as thin as 1 nanometer.

Vias are printed and can be placed without restriction in lower layers.

The assembly uses a solid core to control thermal expansion eliminating mechanical stress on integrated circuit die and spreading heat.

The chips can use flip chip or other bonding attachment method to the assembly.

The number of layers of stacked chips and layers is unlimited.

The metalization can be fabricated with traces much less than 25µm wide and 25µm spaces.

Although originally designed to manufacture ultra-high density capacitors, the first two markets being targeted for this technology are the capacitor industry and high-volume electonics fabrication. Ultra-high density capacitors will follow, with the automotive industry slated next, and ultimately universal personal electronic devices (UPED). A detailed paper about 1st Lighten the Load's technology, licensing opportunities and future plans is available.

Licenses for the technology are now available, and Kelly reported that discussions are in the works with several companies and investors to set up a pilot manufacturing line. I’ll be sure to follow this one as it grows. F.v.T.

Weekend 3D Buzz

I know - I KNOW! I missed my first Friday, and I felt just terrible about it. But hey, I have a valid excuse — several, in fact. I finally sold my house after 11 months on the market (29 showings in January alone, and 9 in February - do the math). So I took some time to get organized for the move, which will happen in about 6 weeks.

In addition, I started to work on the next phase of my 3D plan, of which this blog is merely one dimension. That's all I can say for now, but I'm hoping to have an unveiling of sorts just befor the Device Packaging Symposium in Scottsdale - which is only 2 weeks away. (I'd better get cracking!).

So if things appear to slow down for a few weeks, please stay tuned. A lot is going on behind the scenes - and this is just the quiet before the storm. In the mean time, keep the 3D news coming this way! I'll do my best to keep up.