Filled vs. conformal vias: the consensus

Dr. Zhang, I think we have reached a verdict.

Bob Patti wrote in to confirm Anonymous Caller’s statement regarding polymer-filled, copper-lined TSVs, and also provided some additional data to support his comments. I’ve taken the liberty of paraphrasing his comments here:

With the caveat that he is not a “big fan” of conformal vias, and merely providing data, Bob stated:

“Certainly filling vias with a polymer makes sense to keep material from being trapped and depending on what processing may need to follow, it may be required. A via-last interposer might be a better solution. However, Dr. Zhang's question was is it possible to metalize both sides without filling, apparently it is, shown here in this ZyCube presentation (see slides 29-30, the CIS pictured is from Oki.)

At Tezzaron, we only use filled tungsten via first (middle) processes. I don't think copper via-first is a good alternative, except for interposers. Tungsten TSVs are, at best, limited to ~20µm depth, so copper is (at least currently) the only alternative for vias needing to go more than ~20µm deep. So interposers really must use copper. The issue with filled copper at high aspect ratios and/or large diameters is the exposure to thermal cycling. An interposer will not be exposed to numerous 300-400°C temperature cycles, as a copper via-first chip would be. So interposers are far more likely to tolerate filled vias.

Most memories that I am familiar with, other than our own, are via-last copper. I think they are also conformal, but I could be wrong. This makes them look like the Oki sensor."

So in general, the consensus is that as long as the via formation occurs after the metallization layers, as in via last for CIS, or certain interposer applications, a conformal via is fine. Otherwise, the via should be filled with something: copper, tungsten, or polymer. Got it. -- F.v.T.

A final (?) word on filling TSVs

Now look what I’ve started. After posting Bob Patti’s solution for performing UBM with conformal TSVs, I got a phone call from a 25 year industry veteran who prefers not to be identified, but who disagreed with Bob’s response. He maintains that when forming TSVs in a via-first approach for the purpose of silicon interposers, they must be either completely filled with copper, or lined with copper and filled with either a polymer material or solder, because if you attempt to put a redistribution layer or UBM layer on without filling them, “all the junk” will fill the via. He also noted that in the case of via-last formation for CMOS image sensor applications, there is no need to completely fill the via. I forgot to ask him if the same applies with DRAM memory stacks, which is Tezzaron’s area of specialty, so I’m thinking we may not have heard the last of this discussion.

Although a purely coincidental happenstance, yesterday’s debate turns out to be the ideal lead-in for my next announcement. Beginning July 6, and running through July 24th I will be moderating the BrightSpots 3D IC Forum, hosted by MCA Public Relations in cooperation with SemiNeedle, which will enable industry professionals to participate in an active discussion exploring the key issues surrounding 3D ICs from design to manufacture. The online round-table format offers a platform for continuous dialogue that extends the life of a traditional panel event and features a panel of industry experts ready to discuss critical issues associated with 3D IC technology initiated by questions from the public. To join the online discussion or log on to monitor progress, visit www.semineedle.com/MCA3DIC. You can also monitor BrightSpots-related activities on Twitter under the hash tag: #MCA3DIC. I’m very excited to be a part of this event, and look forward to covering it on my blog. – F.v.T.

TSV copper fill: is it necessary for UBM?

In response to a recent post about the whether/when it is necessary to completely fill TSVs, or sufficient to line them, I received an inquiry from Dr. Zhang of IME, where he has been researching with TSV formation for 2 ½ years. According to Zhang, he hasn’t been able to build reliable vias without completely filling them (either with all copper or copper liner + polymer or other materials). He cited an illustration from a paper he co-authored for ECTC 2009, titled Package Development of Through Silicon Via (TSV) Interposer Technology for Large Die (21x21mm) Fine-pitch Cu/low-k FCBGA (proceedings pp. 305-312) which demonstrates that it is necessary to completely fill the vias in order to perform front- and back-side metallization/UBM (under bump metallurgy). The example shown here is performed for a TSV interposer application.

Zhang inquired how it is possible to do front-side and back-side metallization/UBM without filling the vias. As I am an industry journalist and not a research scientist, I decided to pose the question to my readership, both to help Dr. Zhang further his research, and also to help create the atmosphere of interactivity I’m hoping to inspire with this blog.

If any of you can provide an answer to this question, please let me know, and I’ll post the response here. – F.v.T

More about UBM for conformal TSVs

In response to the previous post, Bob Patti of Tezzaron Semiconductors weighed in with a solution to performing under bump metallization (UBM) on conformal (lined rather than filled) TSVs. Patti says that Dr. Zhang is correct in stating that you can't put UBM on top of a conformal TSV. However, he suggests solving the issue by placing a pad next to the TSV and putting the UBM there. Thanks for your help, Bob! - F.v.T.