Walker confirms; SATS Industry is healthy

Yesterday's post resulted in an email from Jim Walker, Research VP, Semiconductor Manufacturing, Gartner Dataquest. I've known Jim for several years, as he served on Advanced Packaging magazine's advisory board, and have often consulted with him on market research for the Semiconductor Assembly and Test Services (SATS) sector. I thought his comments should be shared with my whole readership as more than just a comment to the original post. So with his permission, I've decided to post his email here, in its entirety:

Françoise –

Thanks for writing your blog on the SATS market today. It appears that someone in the press was taking 2 separate recent reports we wrote on the SATS market and combined them into one, resulting in confusion for the readers. One report on the SATS market share for 2008 (which you referenced) dealt with revenue numbers. The other report, by David Christensen, our factory database analyst, discussed manufacturing facilities and the square footage of factory space that has and will be changing over the next year regarding IDM and the SATS companies. I agree with your assessment that the SATS industry is healthy and not in 'dire' straights.

I have received a lot of emails concerning the articles and wondering what was going on with the industry.

Regards,

Jim Walker

So there you have it, straight from the source. Thanks for clarifying that, Jim. -- F.v.T

Is SATS revenue declining or relocating?

What’s that you say? The SATS sector is set for further declines? Really? Or is that yet another negative perspective being expressed by the trade press? Ok, one publication’s headline reporting Gartner’s latest findings grabbed my attention, while I experienced that “oh no here we go again” feeling in the pit of my stomach. Further reading on other industry sites unearthed a more balanced picture. Yes – numbers are down due to the global economy. Nothing earth shattering there. But the solid numbers reported past revenue from 2008 backwards, and anything going forward is purely speculative.

Let’s talk about what’s really happening. Although the SATS sector reported losses last year, they still outpaced the overall semiconductor industry. In fact, several of the OSATS providers – STATS ChipPAC, Unisem, and Powertech all reported growth over 2007. The expected 40% drop in back-end semiconductor manufacturing capacity is reportedly expected at IDMS not the OSATS providers. That number has more to do with IDMS and OEMS adopting an outsource model and shifting the work to packaging houses. As a result, Gartner predicts a 60% capacity increase for the OSATS in the same time frame. In fact, ASE recently reported being awarded a sizeable contract by Intel. One big enough, in fact, that it is likely to boost ASE’s revenues past the expected level. The contract is reportedly due to Intel’s closing of in-house packaging and test facilities.

According to an article I read in Taiwan Economic News, other IDMS such as NXP Semiconductor, Renesas, and Toshiba are expected to follow suit; and other OSATS will benefit. So rather than an overall loss in revenue wouldn’t this be more appropriately termed a shift in revenue? And don’t all parties ultimately benefit as resources are conserved in one place as they are expanded in others? I think they call this restructuring, and at the end of the day, the industry as a whole might just benefit.

So how does this relate to 3D technologies? Clearly, OSATS play an integral part in market adoption of 3D IC integration technologies. I suggest that volume production of 3D WLP and 3D IC stacking using TSVs could be the missing variable to tip the scales in the favor of OSATS who invest in those production capabilities. When numbers are reported next year, will the companies who took on the challenge be the ones reporting growth? That’s what I want to know. – F.v.T.

Can cost-sharing accelerate 3D IC commercialization?

I’ve been talking a lot about the collaborative efforts in the form of open and closed consortia and joint development agreements that seem to be carrying 3D IC integration forward to market adoption. Another approach is a multi-project wafer program, in which participants cost-share to build multiple device prototypes on a single wafer. The intention is to bring the resulting prototypes to commercialization more quickly and at a lower cost to each member than if they were developed individually.

One such program is Tezzaron Semiconductor’s multi-project wafer program, first reported a few months back on Phil Garrou’s 3D blog, Perspectives from the Leading Edge. According to Garrou’s post, the project would allow up to 10 participants to buy a share of wafer real estate for the purpose of developing prototype 3D IC logic devices. The intention was for each participant to design its own 3D logic device, which would be built in Tezzaron’s proprietary FaStack process. Each logic device would then be integrated with a Tezzaron 3D DRAM to create a hybrid memory/logic 3D-IC. Hmm, I thought, cool approach. I need to find out more.

Unfortunately, the project went dark,(it was initially sponsored by DARPA, and mum’s the word when government agencies are involved.) However, the embargo has lifted, and last week I had a lengthy chat with Gretchen Patti, of Tezzaron Semiconductor. While she couldn’t reveal details of specific devices being tested in 3D by participants, she did say they primarily fell into one of two categories; processors and sensors. For the non-techies among us (like me), Patti offered a simple description of the process.

Figure 1 illustrates how two levels of logic are being built on one wafer. Suppose that the two red squares belong to a participant prototyping a processor, the two yellow squares belong to a participant prototyping a sensor technology, etc. The processor is designed with two layers of circuitry. One layer is built in the red square on Side 1, the other on Side 2. Similarly, the sensor is designed with two layers of circuitry that are built in the two yellow squares. Now we build a whole bunch of identical wafers. Each wafer is stacked face-to-face on an identical wafer. In this way, the sensor dies line up, and the processors line up. When the wafers are bonded, the sensor’s two layers of circuitry become a single circuit, and so do the processor layers. The final project wafer consists of different logic devices, each designed by a different participant.

Next, logic devices are then stacked on a Tezzaron 3D DRAM wafer, which was also created as a wafer-to-wafer stack using tungsten-filled TSV interconnects. The final output is various logic-on-memory devices, assembled in a die-to-wafer process using TSV interconnects (Figure 2). One of the benefits of multiple projects being designed using the same memory wafer is that the logic is then designed to interface with a standard memory, so that although the memory wafer is not customized to each device, it attaches as if it was.

According to Patti, the project has taken on a life of its own, and has grown beyond the original intention to include 19 participants from both the public and private sector, including several universities (U. of Pittsburgh, U. of Michigan, and Johns Hopkins, to name a few.)

“We couldn’t believe the response,” she said. “We didn’t even publicize it.” They ended up with 30 applicants, more than twice as many as they expected. There’s no doubt about it, it’s an attractive alternative for companies who can’t swing their own processing costs, but want to test their product to see if it works in 3D. “People are ready,” notes Patti. I’ll say. Look for more on this as I talk to some of the university participants about specific projects. – F.v.T.