The TGIF 3D Buzz

As my first official week blogging about 3D IC packaging technologies winds down, I'm thinking a Friday wrap-up is in order, and should probably become a regular event. (Being a fly-by-the-seat-of-your-pants kind of person, it's only natural that this blog takes shape as the opportunities present themselves, don't you think?)

Trolling the web for 3D info this morning, I unearthed what I consider to be some noteworthy points of interest. First of all, I found out that NEXX Systems has become a member of SEMATECH's 3D Interconnect Program at the University of Albany's College of Nanoscale Science and Engineering. Specifically, the collaboration will focus on developing high-yield, low-cost copper electroplating processes to enable high-density TSVs. Another thumbs-up for the effectiveness of collaboration.

Next, Ziptronix announced it is developing licensing sGtrategies for it's ZiBond low-temperature covalent bonding and DBI direct bond interconnect technologies across the supply chain, because according to CEO Dan Donabedian, each link in the chain including EDA tool venders, equipment manufacturers, OEMS, IDMS, chip manufacturers and foundries, stand to gain something from these processes. Look for an in-depth interview on these developments next week.

Two additions to the event calendar include MEPTEC's Semiconductor Packaging Symposium, which, among other things, touches on latest developments in 3D technologies that have made it to full production: PoP stacks, and TSV for CMOS image sensors; and EMC3D Consortium's Asia Tour, which will focus on latest advancements in 3D integration using TSV technology from trends and roadmaps, to performance requirements, cost-effective applications and more.

And finally, while she says it's not "new" news, Gretchen Patti, of Tezzaron Semiconductors, passed along an interesting paper she penned that's worthy of attention as it touches on an advantage of 3D ICs that I had yet to see listed among the usual laundry list of benefits. Evidently, by nature they offer security benefits in two ways. Due to the layered manufacturing processes, their circuitry is virtually impossibly to decipher during manufacture, and fully assembled 3D ICs defeat reverse engineering. For the full story, download 3D-ICs and Integrated Circuit Security. - F.v.T

3D technology research gets another shot in the arm

It looks like it's 3D to the rescue again. I love it. Yesterday, a collaboration was announced by Semiconductor Research Corp. and Georgia Tech that involves the creation of the Interconnect Packaging Center (IPC). The center will be located at Georgia Tech in the Marcus Nanotechnology Building, and will involve the combined efforts of programs at Georgia Tech, Harvard, The University of Texas at Austin, Iowa State University and Singapore's Nanyang Technological University (NTU).

The goal is to develop interconnects that have improved communication between different chips via packaging while achieving an overall reduced chip footprint. And joy of joys, half of the research will focus on new 3D technologies.

This is the second 3D-focused, industry-academia project operating out of Georgia Tech. The 3D All Silicon System Module (3DASSM) Consortium, set to launch early this year, is a combined effort of Georgia Tech’s Microelectronics Packaging Research Center (PRC), the Fraunhofer IZM, KAIST, and (to date) 14 participating companies. Unlike the new IPC, the focus of this work is on packaging, not 3D ICs, and involves work with silicon interposers, wafer-level packaging, and thin-film embedded components to ultimately integrate the IC, package and board seamlessly.

So while not directly related to the collaboration with SRC and Georgia Tech, it certainly poses some interesting synergies. Rao Tummala must be dancing in the streets.

SEMIspice: Five reasons to exhibit during a recession

Be sure to check out SEMIspice: Five Reasons to Exhibit During A Recession. Tom really hits the nail on the head. There's never a more important time to maintain a vital presence in the industry than during a financial crisis. There are certainly other places to tighten the belt than your marketing budget.

Oerlikon streamlines for 3D and solar

Oerlikon’s double-barrel news about the sale of its Oerlikon Esec business unit to BESI, and expected management buyout of its etch unit brings to fruition strategic plans I got wind of in October at SEMICON Europa. At that time, Sven Jarby, who heads up marketing and communications for Oerlikon Balzer’s Coating, alluded to the company’s strategic plans to focus on applications that appeal to its core competencies; thin film and coating for TSV processes and solar panels.

By divesting itself of its only traditional back-end semiconductor unit, the wire and die bonder business, Dr. Uwe Krüger, CEO of the Oerlikon Group, says “Oerlikon has significantly reduced its exposure to the cyclical semiconductor market.” It becomes more apparent as companies align themselves vertically that knowing what your company’s core competencies are and focusing on those is a good way to carve a niche in the future of the industry.

The other ponderable question is what BESI will do with Oerlikon Esec’s die bonder division. The organization already holds a strong market position in the die bonder arena with Datacon. According to a press release from BESI, the Esec brand name will be retained, and plans are underway to leverage synergies between the two companies. I'll be curious to find out what becomes of the Oerlikon Esec/Muehlbauer alliance that was announced in November, which was intended to provide turnkey solutions for the smart card module industry. It’s no secret that Datacon is firmly established in RFID technologies. Will this make for strange bedfellows or will it be a merging of the minds? I’ll be keeping my eye on this one.