Lisa McIlrath, R3 Logic: design tools for 3D IC are on the way

Mea culpa. I may have jumped to conclusions in yesterday’s post. Although it appears to those developing 3D IC integration processes that the design community hasn’t been heeding the call for the much needed design tools, after talking with Lisa McIlrath of R3 Logic, I realized there’s a lot more to it than that. In fact, the message has been heard, but these things are more convoluted than we think. In fact, it's a bit of a cart-before-the-horse situation. How can design tools be developed until the process technologies, characterization, and paramaters have been determined, and prototypes tested? For that matter, each customer is likely to establish its own design rules.

Consider that 3D IC integration is still a very new field, and that everyone is very much in what McIlrath called “pathfinding mode”; exploring different designs before having the parameters figured out. She said that there’s lots of advance work being done to discover different customer needs. Design tools needed now for CMOS image sensors and soon for stacked memory may not necessarily turn out to be the same ones needed down the road for heterogeneous integration. Unfortunately, it’s still not clear what the winning applications will be.

For large companies, there's not much incentive to invest in development until the picture is clearer and the market is big enough. However the buzz is that Cadence has been some internal development, and and Synopsis and Mentor are sending some of their people to Friday’s 3D Integration Workshop at DATE 2009, in Nice, France. Clearly, the interest is growing.

McIlrath said that although it might be risky and difficult for small companies to set a course on a tool that may not be adopted, it’s also easier for them to be agile as the market shifts and changes. For example, R3 Logic discovered a need by the research community for a layout editor, so they partnered with MicroMagic to develop one. (Tezzaron Semiconductors, pioneers in manufacturing stacked memory with TSVs uses the tool, and has endorsed it.) This week at DATE 2009, McIlrath says R3 Logic will be showcasing a 3D floorplanning tool scheduled for install this summer. Additionally, last month, the company announced a collaboration with ST-Microelectronics and CEA-LETI to develop a full 3D design flow.

McIlrath says that although it’s regrettable that there aren’t more tools out there and available, she doesn’t agree that the lack of design solutions, or test for that matter, is a blocking factor in TSV adoption. “3D integration is going to go ahead with or without any particular player,” she said. “The design tools are coming. Our goal is to find the most appropriate tools to suit the needs of the users.” – F.v.T

The TGIF 3D Buzz

As my first official week blogging about 3D IC packaging technologies winds down, I'm thinking a Friday wrap-up is in order, and should probably become a regular event. (Being a fly-by-the-seat-of-your-pants kind of person, it's only natural that this blog takes shape as the opportunities present themselves, don't you think?)

Trolling the web for 3D info this morning, I unearthed what I consider to be some noteworthy points of interest. First of all, I found out that NEXX Systems has become a member of SEMATECH's 3D Interconnect Program at the University of Albany's College of Nanoscale Science and Engineering. Specifically, the collaboration will focus on developing high-yield, low-cost copper electroplating processes to enable high-density TSVs. Another thumbs-up for the effectiveness of collaboration.

Next, Ziptronix announced it is developing licensing sGtrategies for it's ZiBond low-temperature covalent bonding and DBI direct bond interconnect technologies across the supply chain, because according to CEO Dan Donabedian, each link in the chain including EDA tool venders, equipment manufacturers, OEMS, IDMS, chip manufacturers and foundries, stand to gain something from these processes. Look for an in-depth interview on these developments next week.

Two additions to the event calendar include MEPTEC's Semiconductor Packaging Symposium, which, among other things, touches on latest developments in 3D technologies that have made it to full production: PoP stacks, and TSV for CMOS image sensors; and EMC3D Consortium's Asia Tour, which will focus on latest advancements in 3D integration using TSV technology from trends and roadmaps, to performance requirements, cost-effective applications and more.

And finally, while she says it's not "new" news, Gretchen Patti, of Tezzaron Semiconductors, passed along an interesting paper she penned that's worthy of attention as it touches on an advantage of 3D ICs that I had yet to see listed among the usual laundry list of benefits. Evidently, by nature they offer security benefits in two ways. Due to the layered manufacturing processes, their circuitry is virtually impossibly to decipher during manufacture, and fully assembled 3D ICs defeat reverse engineering. For the full story, download 3D-ICs and Integrated Circuit Security. - F.v.T

Mark your 3D event calendars

A few months back when Ziptronix first revealed details about its direct bond interconnect(DBI), CEO Dan Donabedian told me that one sign the market was ready for 3D integration processes was the demographic of attendees at conferences devoted to 3D IC packaging technologies. Rather than application and process engineers, he said, the seats are now occupied by marketing and business development people. So naturally that was the audience he targeted in his presentation at November’s 3-D Architectures for Semiconductor Integration and Packaging conference.

As we draw closer to adoption of these technologies, it’s important for all of us non-techies to get familiar these new processes, applications and market drivers. There are an assortment of upcoming events in the offering sessions and presentations on 3D.

SMTA’s Pan Pacific Microelectronics Symposium, Feb 10-12 on the island of Hawaii, offers a session on 3D assembly that I would suggest attending:

System-on-Wafer by The 3D All System Silicon Systems Technology consortium (Georgia Tech, Fraunhofer IZM),

Advanced Electrodeposition Technologies for 3D integration by Rozalia Beica and Paul Siblerud, Semitool, Inc.

Copper Electroplating Process for Next Generation Core Through-via Filling Stephen Kenny and Bernd Roelfs, Atotech Deutschland GmbH. I also hear the Luau is not to be missed.

Judging by the line-up at this year’s IMAPS International Device Packaging Symposium, the program organizers were on the ball with 3D topics. For example, a half-day professional course titled 3D Integration: Technology, Applications & Markets for 3D Integrated Circuits, lead by Phil Garrou of Microelectronics Consultants, is recommended for marketing and management people. As is the second half-day session lead by RPI’s James Jian-Qiang Lu titled 3D Integration and Packaging Technologies, Assessment, Status and Applications. And definitely don’t skip the And definitely don’t skip the 3D panel discussion: 3D Integration Technologies, Applications, and Roadmaps. There are also a plethora of sessions to choose from on TSV processes and other methods of 3D interconnect. It should be a great event. It was last year!

And finally,coming up in Nice, France on April 24th, Design Automation and Test in Europe (DATE) 2009 will tackle roadblocks to 3D adoption; process technology, architectures, esign methods and tools, and manufacturing test solutions. – F.V.T