Endlich Freitag! 3D Buzz

Guten Tag! It’s Friday already? I’m not sure where that week went, but I managed to gather some interesting 3D tidbits throughout the course of it. Let’s begin with Sally Adee’s 3D coverage of IEEE’s International Solid-State Circuits Conference that took place in San Francisco this week.

It seems the big news was progress in 3D integration using TSV for all types of memory; right on schedule with Yole Développment’s predictions of TSV chip stacking for DRAM beginning in 2009 and ramping to high-growth in the 2010-2013 time-frame. Toshiba reportedly won the prize for having the first available product with its 3D stacked image sensor. Additionally, Infineon reported success in developing their second-generation wireless pressure sensor interconnected with TSVs on two levels of the 4-layer chip stack: the MEMS sensor and the transceiver.

I was excited to see the announcement of Tessera’s licensing of it µPILR technology to Kinsus, because I’ve been following the progress of the technology since I first saw Vern Solberg’s presentation at IMAPS in San Diego in 2006. The process calls for stacking logic, memory, flash and DRAM with low-profile, pin-shaped contacts, replacing traditional interconnects such as solder balls on semiconductor packages The plan is for Kinsus, a Korean-based package substrate manufacturer to make and sell substrates base on µPILR technology. It's always cool to see the baby bird find its wings and take off.

There was also some buzz about 3D chip stacking equipment in development. From the Netherlands and Austria, came TNO’s announcement of collaboration with Besi/Datacon to develop a production-level die bonder for 3D chips stacking for TSV manufacturing based on Datacon’s successful 8800 flip chip bonder. The targets chip-to-wafer processes with the intention of developing a machine that starts out with processed wafers without vias and finishes with complete die stacks.

Not far away in Switzerland, Kulicke & Soffa/Alphasem is getting ready for the SEMICON China launch of its new high-production die bonder for 3D chip stacking. According to Richard Boulanger of K & S/Alphasem, the company’s tool will focus on high-performance stacked die applications first but will extend in other markets later.

There’s a lot more to both these stories, and I still have lots of questions that need to be answered, so look forward to more on these developments next week since the work day is already over in Europe. Schonen Wochenende!

Other 3Ds: HIDING DIES/HERMES projects update

Tuesday’s post, which referenced the Fraunhofer IZM’s work in embedded die technologies to achieve 3D packages, reminded me that I hadn't seen much in the news about it since the announcement of HERMES partnership with Flip Chip International last July, following the launch of FCI’s Embeddable Die Customization (EDC) technology. HERMES is the follow-on project to HIDING DIES, and is focused on the industrialization of embedded die processes. The goal was for FCI’s technology to provide part of the infrastructure that would help take HIDING DIES from the development stage to high-volume production. With HERMES’ one-year anniversary coming up in May, I decided it was more than time to weigh in on the progress.


Here’s what I learned. In October, Lars Boettcher, Dionysios Manessis, Andreas Ostmann Stefan Karaszkiewicz and Herbert Reichl, members of the HERMES project research team, received the 2008 Outstanding Paper Award at the 3rd IMPACT and 10th EMAP Joint Conference in Taipei, Taiwan for “Embedding of Chips for System in Package Realization – Technology and Applications”.

In addition to offering an overview of the generic chip-in-polymer technology, the paper discusses development of the technology further to realize 3D SiPs, and new challenges that must now be addresses as a result. According to the paper, a related goal of the HERMES project is to unearth and address these challenges, and once they are validated at prototype level, to develop a business model that would merge PCB and component manufacturing lines to produce these high-density devices at low-cost.

It appears that the team is ready to tell the next chapter in the story at IMAPS Device Packaging Symposium, on Thursday, March 12, from 9-9:30am. If you’re interested in following this progress, be sure put “Chip Embedding Technology – New Technological Challenges for a Reliable System-in-Package Realization" on your technical agenda. Somebody save me a seat up front. - F.v.T.

Other 3Ds: The many uses for LCP

Last fall before SEMICON Europa, Andreas Ostmann, manager of the embedding and substrate technologies group, Fraunhofer IZM, spent some time with me explaining what he decribed as 3 distinct levels of 3D packaging. The first was die stacking through TSV. The second was what he termed a reconfigured wafer of molded single chips, citing as examples Freescale’s redistribution chip package (RCP), and the embedded wafer-level ball grid array, (eWLB) a collaborative effort of STATS ChipPAC, STMicrolectronics and Infineon. The third involves embedding chips into organic materials using PCB technologies. Ostmann's own work at the Fraunhofer IZM, chip in polymer, via the Hiding Dies and Hermes programs, falls in this category.

In this third category, I’ve been following the work of a research group at Georgia Tech, who is developing an embedded 3D technology using liquid crystal polymer (LCP) as a base material. Due to its dielectric properties, flexibility, and near-hermetic nature, LCP can be used as a substrate, dielectric and sealant for 3D construction, making an all-LCP package a viable option. Swapan Bhattacharya and John Papapolymerou, of Georgia Tech’s School of Electrical and Computer Engineering have been leading this research, and have contributed a series of articles to Advanced Packaging magazine, outlining their work. Four of six parts have been published:

3D LCP Package Technologies Parts 1-4:
Part 1: Embedded Actives
Part 2: Laminated Thin Film Resistors on LCP
Part 3: Power Dividers on LCP
Part 4: Electroless Plated Thin-film Resistors on Organic Substrates

I'm looking forward to Parts 5 and 6, to round out the series. - F.v.T.

The Other 3D Packaging Technologies

While TSV developments continue to attract media attention as the rock star technology of 3D integration, it’s important to remember that it’s not the only game in town. As a member of said media, I must admit that it’s easy to get caught up in all TSV all the time, because it’s been exciting to follow, and there are a lot of elements that need to fall into place for market adoption. Therefore, it’s an easy target. But what about other 3D technologies that are making progress? Any journalist (or blogger) worth his or her salt knows that the best story ideas require a little digging, so here goes. This week I’ll focus on bringing readers up to date on some of these.

Vertical Circuits’ Vertical Interconnect Pillar Technology
Abbreviated to the acronym, VIP (clever, don’t you think?), this technology was developed as an alternative to both wire bond and TSV, overcoming scaling limitations of the former (up to 100 die have reportedly been proven) and design and cost limitations of the latter. VIP is actually the final step in a series of process steps that begins with standard die in wafer form. Die pads are re-routed to the periphery, and the die goes through an insulation process. The wafer is then thinned and die are singulated. Next the die are stacked and laminated together with an adhesive. Finally, conductors are jet dispensed on the edge of the die stack using Asymtek’s high speed, high accuracy jetting technology. The process involves existing equipment, and can be integrated into any existing back-end assembly line. Target applications include memory modules, embedded memory, and system-in-package.

This company and its technology made recent headlines with the announcement of its strategic partnership with DISCO, known for its high volume manufacturing (HVM) backgrind and dicing tools. As VCI’s process relies on wafer thinning and dicing techniques, the partnership allows them to offer an established toolset to the IDMs and packaging companies that license its technology.

Look for presentations from VCI at several upcoming industry events including IMAPS Device Packaging Symposium, ISTC/CSTIC 2009 (part of SEMICON China), 2009 MRS Spring Meeting, and ECTC 2009. – F.v.T.