3D innovation: prevention or cure?

In his editorial yesterday, Steve DeCollibus, managing editor of Semiconductor Packaging News, offered some food for thought about the concept of the semiconductor industry innovating its way out of this downturn. To illustrate his point, he tracks the evolution of the integrated circuit itself – a technical innovation that took 80 years to complete.The point he makes is this: true innovation takes time, dedication, collaboration, and full participation of everyone from academia and R&D, across the entire supply chain. It’s not something that can be done, as he puts it “on demand.” I couldn’t agree more.

Innovation shouldn’t be seen as the antidote, or cure to the current economic pandemic. Rather, ongoing treatment seems to be much a much more potent measure against the disease. For example, 3D integration technologies have been the innovation flavor-of-the-month since long before the current economic disaster hit. Is it by pure coincidence that those companies who continued to push forward and invest in these technologies are the ones who were more resistant to the downturn virus? I’m talking about start-up companies like Alchimer, Replisaurus and Imbera, who managed to raise venture capital to develop their technologies; and established equipment manufacturers like SUSS MicroTec, Surface Technology Systems, and EV Group, who have all recently reported installs in both research and production settings. According to Steve Dwyer, director of sales, North America, EVG, in the past 3 weeks, EVG has received 6 tool orders for TSV processes in North America alone, 4 of which are headed for production lines, while the other two will go to research settings.

Although it may seem that the “Pollyannas” of the industry (myself included) have been dishing out the “innovate out of the downturn” mantra as a way to bolster morale, it’s not without basis. However, perhaps a more accurate explanation is that during a downturn, there is less time spent manufacturing and shipping product, and more time to focus on innovation. The companies who took advantage of that time seemed to be hit less badly by the downturn, and those who were already innovating and continued on that path were the most resistant to the effects of the downturn. After all as, Benjamin Franklin once said, an ounce of prevention is worth a pound of cure. – F.v.T

Semi Standards – a 3D conundrum?

I got into an interesting conversation recently with Steve Dwyer, of EV Group, about the puzzling situation 3D IC integration is posing with regard to existing Semi Standards, and those yet to be established as 3D IC integration processes are developed.

Take, for example, the standard for wafer handling. Dwyer explained that the current standard calls for a process wafer to be returned to the same slot in the FOUP where it came from. But with temporary bonding for thin wafer handling, the input comes from two separate FOUPs, and the output is the two wafers bonded together, so one FOUP winds up with an empty slot, thereby breaking the standard for handling wafers. Clearly, the standard was set based on single wafer processes, and didn’t consider future possibilities of multiple wafers being combined into a single processed wafer.

Additionally, when it comes to establishing standards for 3D IC integration processes, all the different processes being developed — via-first, via-early, and via last; front side approaches vs. back-side approaches; wafer-to-wafer, chip-to-wafer and chip-to-substrate — will need to be considered.

So what’s the hurry? Is the establishment of standards for 3D IC integration critical for market adoption to take place? Would it be better to hold off until the processes shake out and we see what sticks? Consider also that if multiple approaches are adopted, then standards will need to be set to accommodate different options. “Until the industry works out what it wants to do, we need the flexibility,” notes Dwyer.

I posed this question to Sitaram Arkalgud of SEMATECH’s 3D interconnect program, and Rich Brilla, of the College of Nanoscale Science and Engineering (CNSE) at the University at Albany. Brilla noted that in addition to standards focused on equipment and processes, design ground rules are also needed. For example, knowing where alignment marks should be for wafer to wafer and chip to wafer processes is critical. Part of the work being done by SEMATECH at CSNE will help to establish these standards.

“It takes ages for standards to come together. It’s a voyage of discovery,” notes Arkalgud, adding that this work-in-progress approach to standards is still better than having nothing at all. “3D can revolutionize the industry, but needs standards in order to make it happen, otherwise it will delay the adoption of technology,” he said; a sweeping statement perhaps, but his point is well taken. Without standards to bring the technology to high volume, it runs the risk of just being a niche market. – F.v.T.

Another step forward for EDA Tools

I have to admit, I’ve always had difficulty trying to wrap my head around software, especially design tools. So I’ve come to have a deep respect for those individuals charged with the task of designing the design tools themselves. Not only do they need to be able to visualize the end result, they have to work backwards to anticipate the steps required to get there, and then figure out a way to archive that knowledge for later use. In essence, before a design tool can be designed, the methodology of the steps to achieve this must be established. Then, EDA tool designers create a tool based on these established methodologies to be able to automate the design processes for manufacturing.

Current 2D tools have no notion of a 3D hierarchy and thus no way to build IP libraries for 3D. To design 3D ICs, designers had to resort to tricking 2D tools by renaming design layers or creating multiple copies of standard cell libraries. This “design-by-hand” works fine for 2.5D structures like CMOS image sensors and homogenous 3D DRAM memory stacks, but as Lisa McIlrath, of R³Logic, pointed out during the panel discussion at DATE 2009, logic/memory stacks and true heterogeneous integration will need fully functioning 3D design tools.

Understanding the ramifications of this is what makes R³Logic's latest achievement of that much more noteworthy. The company was recently awarded a patent for “methods and systems for computer aided design of 3D integrated circuits”. According to a company statement, the patented invention comprises both the method of defining a 3D technology file that can incorporate one or more 2D wafer technologies corresponding to different tiers in a 3D stack, and that of defining a 3D hierarchical structure for functional blocks within a 3D system. Managing multiple design libraries while properly handling IP blocks that reside on more than one tier is crucial to 3D system design, notes R3Logic, whether at the circuit layout or at the system architecture level.

Achieving this milestone brings th 3D design pioneer another step closer to proving the industry with the tools they’re seeking. I offer my congratulations and look forward to hearing more about it. – F.v.T