The post-fab process debate for 3D ICs: foundry or OSATS

Inquiring minds want to know: who is going step forward and claim ownership of post-fab processes for 3D IC stacking using through-silicon vias (TSVs)? This has been a topic of debate for some time, with no real solution, although plenty of reasons why one or the other is the way to go, depending on who you talk to. Here's my understanding of the situation.

First of all, there’s a hodge-podge of process flows being tossed around. Some are more suited to a fab environment, and others are more suited to an OSATS environment. Additionally, some approaches are suited to specific applications. For example, CMOS image sensors, the first TSV application in production, uses a via-last approach that requires no adaptation to front-end technologies. However, memory stacks are targeting via-first due to a lower cost-of-ownership.

To grasp it all, it’s important to understand the basic concepts – creating the vias themselves, and stacking the die. The EMC^3D Consortium has developed two proprietary process flows, iTSV and pTSV, both currently based on a die-to-wafer stacking process rather than wafer-to-wafer. iTSV is a via-first approach, in which vias less than 10 microns are formed after CMOS process, but before BEOL processes. Alternatively pTSV is a via-last approach, with vias formed before bonding, but uses the packaging infrastructure.

According to Tom Gregorich, VP of packaging at Qualcomm, there are two process flow options for creating TSV through-silicon stacks (TSV TSS) using a via-first approach. In the die-to-wafer flow, stacking happens during post-fab processing, and the diced die stack is treated as a single die in the assembly processes. In a die-to-substrate flow, the diced top and bottom bumped die arrive at the assembly house independent of each other, and are stacked directly on the substrate medium at assembly house.

In either of these flows, the processes that happen at the foundry end at via formation, and the flows are identical up to the micro-bumping step. Post-fab processes of thinning, dicing, and stacking can occur either at the foundry, the OSAT or a third, yet to be established location. Gregorich says the difference is that die-to-wafer requires post-fab process to be co-located with the OSATS, due to the fragile and expensive die stack, but with die-to -substrate can be independent of each other. “ TSV/TSS requires a significant expansion of and investment in post fab processing operations,” he notes.

So according to Gregorich, the million dollar question is who will make the investment in post-fab processes, the foundries or the OSATS? Thus far, he says the base of technology is already in the OSATS, and Amkor is investing in the TSS processes. But will foundries who invest in TSV processes also invest in the post-fab processes? TSMC just announced it will ready its 300mm facility for TSV processes by June. Will they take the leap and extend that to include post-fab processes for D2W stacks?

If everyone is right, then it doesn’t seem to be a case of either or, but rather, an application-specific issue. As we often see when it comes to this industry, the solutions are never straight forward. In this case, the savviest of fabs and OSATS will see opportunity in the investment, and both options will be available. Meanwhile, those involved in developing processes, equipment and materials are covering all the bases to ensure what they’re developing can suit all the available scenario: via-first or last; W2W or C2W, foundry or OSAT. That’s my take on the situation. I’m curious to know what others think will happen. ( Don’t be shy – that’s what the comment function is meant to be used for.) – F.v.T.

Following the 3D innovation path to profitability

In last week’s email update, I talked about the pendulum starting to swing back the other way, albeit ever so slightly. It’s little things, such as SEMI’s book-to-bill rising from a frightening .48 to a less ominous .61; to bigger things, like TSMC announcing they will invest in R&D despite a hiring freeze in other sectors. As part of it's roadmap to innovate its way out of the slump, the company claims it will have its 300mm fab ready to manufacture TSVs by June. This is exciting news for equipment and material suppliers who have committed to investing in TSV processes.

Whether or not you're a proponent of TSV, it’s clear that companies who are investing in those technologies are faring better these than those who are hacking away at the bottom line to weather the storm. It seems to be working for SUSS MicroTec and EV Group, who have both invested in developing tool sets for wafer bonding, lithography, and mask aligning for the 3D IC integration market. Last week, SUSS announced an order from Nemotek Technologie for multiple lithography systems to be used for manufacturing the company’s CMOS images sensors (CIS). As CIS was the first application to adopt TSV processes in volume production, this win helps establish SUSS as an equipment provider for CIS.

On the heels of that news, came EV Group’s announcement that they will increase production capacity due to “strong order intake” driven by R&D investment in the 3D IC and nanoimprint lithography markets. EV Group strategically established itself in academia, shrewdly anticipating that while capex spending would fall off in the public sector, universities and research institutes would be investing in 3D IC integration to be ready for the rebound.

In his recent SemiSpice blog post, Tom Morrow recounts the different approaches taken by both Kelloggs and Post to survive the Great Depression. Reading it, I thought of Lam Research and Applied Materials (AMAT), equipment vendors who both offer etch tools for 3D IC applications. See if you can guess who is the Post and who is Kelloggs in this scenario. In December 2008, AMAT made headlines with its launch of the Silvia etch tool, then joining EMC^3D and most recently entering into a joint development agreement with Disco to develop wafer thinning processes for TSVs. The only news I’ve seen about Lam in the same time frame is a layoff of 600 employees in November, and another 375 in March. Both layoffs were part of a plan to reduce Lam’s cost structure. In December, Applied announced a cash dividend, while in April, Lam announced a quarterly loss.

While cost cutting may help the bottom line in the short term, it’s my experience that in the long run, innovation and investment goes a lot further to improve a company’s image and ultimately its bottom line, not to mention establish company moral and loyalty. Kudos to the companies and organizations that choose not only to invest and innovate, but also publicize accomplishments. It gives us all something to strive for. -- F.v.T.

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