What’s your semi lingo IQ?

I’ve long been fascinated with the vernacular of the semiconductor industry, which is riddled with acronyms that can often mean different things whether you’re referring to front-end or back-end applications. Additionally, as 3D technologies have developed, so has a whole new set of terms that are evolving right along with the processes. It certainly makes for interesting discussion, as I found out last week at ECTC 2009 (that's Electronics Component Technology Conference).

For example, SoP can mean small-outline-package or system-on-package depending on who you talk to, and before SiP referred to a system-in-package, it was a single-inline-package (not to be confused with a DiP, or dual-inline-package). And before a system-in-package was called a SiP, it was referred to as a MCM, or multichip module. Confused yet? Jeanne Beacham, of Delphon, and I started joking in the buffet line at the conference. “What’s so great about PoP,” quipped Jeanne Beacham of Delphon. “What about MoM?” I laughed, but then again, it’s entirely possible. PoPs made of multichip packages could be called multichip-on-multichip (MoM). They certainly will be able to do lots more than a PoP (I’ll just leave it at that).

What’s more, we toss around terms like FEOL and BEOL (front-end-of-line and back-end-of-line) and FOUP (front opening unified pod) like everyone knows what we’re talking about. (I actually had to look that one up while writing this. I know what FOUPS are; those orange thingies that hold the wafers before and after processing. I just didn’t know what the letters stood for.)

All kidding aside, settling on a set of terms for 3D processes is actually the first step to standardization, notes Eric Beyne, of IMEC. We were discussing how chip and die are used interchangeably, (specifically in reference to die-to-wafer stacking or chip-to-wafer stacking.) and the confusion it causes for those who distinguish between the die and the chip based on whether it’s bare or packaged. Last year, we were told via first could be further distinguished into via-early (before CMOS) or via-middle (after CMOS but before BEOL). Oh great, there’s another one. (For those about to ask, CMOS stands for complementary metal oxide semiconductor. No wonder we don’t usually write that out.) In any case, Beyne says the ITRS (International Technology Roadmap for Semiconductors) is working to standardize definitions, because classification of technologies is required to define a roadmap.

Incidentally, if someone can tell me what IMEC stands for, the drinks are on me. – F.v.T.

News in 3D: the plot thickens at ECTC

Gossip flies at industry events. But usually as soon as someone tells me something juicy, they follow up with “but you can’t write about that yet.” Do you realize how hard that is? When, WHEN can I tell? Other times, I guess the answer, and can tell I’ve hit the nail on the head by the silent response and look on the interviewee’s face. But still, I’m sworn to secrecy with the promise of being the first to know when the news is ready to go public. I’ve got a few things under my hat at the moment. I’ve been sitting on one scoop for the better part of a year now.

It’s much more fun to be given the inside story and be the first to tell it. For example, I get to be the first to formally announce that Kathy Cook, previously of SUSS MicroTec, has joined Alchimer as business development manager. We talked about recent accomplishments (as in yesterday) for Alchimer, which involved proving thermal reliability of electrografting copper seed on titanium nitrite. According to Frédéric Raynal, product development manager for Alchimer, this is significant because the availability of reliability information has been an obstacle in achieving customer specifications. So the company had a third party perform reliability tests. So far, after 500 thermal cycles, thermal reliability was achieved from -55°C to 125°C. Results of 1000 cycle reliability tests will be available in June.

Additionally, at SEMICON West this year, Alchimer will launch the full AquiVia line , building on last year’s launch of egViaCoat, which replaces the dry PVD process for applying a seed layer on TSVs with electrografting, which is a wet process. The AquiVia “trilogy” completes the wet process, replacing conventional dry process flow for insulation (CVD), barrier (PVD/CVD/ALD), and seed (PVD) layers with proprietary wet-based electrografting, chemical grafting, and electrografting processes, respectively.Remember, you heard it here first. There I feel much better now. – F.v.T.