Tezzaron’s multi-project wafer program: participant perspective

Tezzaron’s multi-project wafer program: participant perspectivesTo follow up with last week’s report on Tezzaron’s multi=project wafer program (MPW), I asked a few of the participants to share information about their part in the project, and the benefits of working in this paradigm. The first respondent was Donald Chiarulli, Professor of Computer Science and Computer Engineering, University of Pittsburgh.

To be considered for the program, potential participants had to submit project summaries outlining wafer “real estate” specifications, along with justification for their proposed project. In the case of the U. of Pittsburg, Chiarulli requested “a 5mm x 5mm die with DRAM stack attached to implement a hardware test-bench for a single hop, routerless system-level-interconnection network architecture.” The goal is to develop a low-latency high-throughput, system-level interconnect that enables the next-generation systems, which have thousands of processors tightly integrated with large memories.

“In this project, we are rethinking system-level interconnection networks for large scale 3D ICs,” explained Chiarulli. To this end, Chiarulli and his team, Prof. Steven Levitan, and graduate student, Kelli Ireland, were allotted a die stack consisting of two CMOS die and two memory die. According to Chiarulli, to emulate a large-scale network in the area provided, processor cores at each node in the network were replaced with simple controller nodes that emulate read, write, and coherence traffic between L1-caches and set of shared L2 caches. “Our work is based on a partitioned bus, with a fan-in/fan-out architecture that takes advantage of the increased interconnection density and shortened wire lengths that are characteristic of 3D integration,” said Chiarulli. So when you read about how one of the drivers of market adoption for 3D IC using TSVs is repartitioning, this is what’s being talked about; a way to leverage high levels of integration that can only be provided by 3D hybrid chip stacking technology.

Chiarulli considers MPW runs, such as this one, critical to computer architecture research. “Simulation only gets you so far and there is no substitute for validating results with prototype devices. Continued support by industry and government in making this run available for academic research is very important.”

I expect to hear from other participants in this project, so stay tuned… ~F.v.T