SEMATECH: hitting 3D head-on

At last week’s SEMATECH technology round-up webcast, Sitaram Arkalgud, director of 3D interconnect, made a comment about 3D technologies that, in my opinion, really brought all the issues swirling around it to one vital point. It was this: as a platform, 3D allows a whole other scheme of processes to be considered that don’t enter the realm of possibilities when you’re dealing with a 2D platform.

By now, those of us who regularly attend 3D events can recite the benefits of moving to 3D using TSV—reduced form factor, increased functionality, higher performance, and lower power consumption, reduced cost, etc. Arkalgud expanded on the cost reduction benefit by pointing out that 3D offers the potential for containing costs at device, die wafer, factory and market levels, which could be powerful going forward. He said that even though adding certain steps may additionally add to the cost structure, the benefits will be realized further down the supply chain.

In 2005, when deciding to invest in an R&D program to develop 3D integration using TSV, SEMATECH began by assessing different options, focusing first on materials, via formation, bonding, and integration. To further narrow these options, they focused on cost modeling, performance, risk, and product requirements; benchmarking tools and processes to achieve this. In 2008, the organization really got into the thick of technology development, focusing on the “nuts and bolts of 3D” using 300mm equipment 3D specific tools. The goal of the program, explains Arkalgud, is to have a test bed for member (IDMs, foundries, suppliers, etc.) evaluations.

So far, Arkalgud reports that SEMATECH’s key processes have been:

TSV reactive ion etch: 1 micron vias at a 20:1 aspect ratio using a non-Bosch process on TEL SP UD.

Dielectric liner, barrier, seed layer: TEO/TaN/PVD cu seend using a CSNE toolset.

Void-free via fill: void free Cu via fill using NEXX Stratus

Bonding of wafer or dies: Cu thermocompression wafer-wafer (W2W) bond on 300mm tools.

Working on thinning and handling of wafers/die

3D –specific metrology: IR scanning acoustic microscopy

Specifically addressing issues with thin wafer handling and stresses caused by backside processing and subsequent bonding, Arkalgud notes that the greatest issues still lies with thermal stresses caused by processing conditions, and material requirements for temporary bonding and debonding methodologies. He says that SEMATECH’s 3D program aims to establish standard methodologies with which to evaluate current processes and materials to create its own data that can be compared “apples-to-apples”, rather than rely on data provided by individual suppliers. The organization is currently evaluating 300mm bonding tools to determine which will be most suited to carry out this work.

Additionally, when it comes to addressing thermal issues with 3D integration, Arkalgud says possible solutions involve using dummy TSVs as heat sinks; developing design tools that dynamically detect where hotspots would be and designing accordingly; or even incorporating channels for microfluidic cooling. This is where Arkalgud’s comment came in about 3D schemes offering new possibilities where 2D falls short. Really, when you think about it, at 2D if we attempt to further reduce form factor while increasing functionality and performance in a 2D scheme, we’re going to hit the same roadblocks in thermal management, power consumption, yield management, cost, etc. While 3D may not have all the answers yet, it certainly opens the door to solutions that otherwise can’t be achieved. – F.v.T.