May Events in 3D

I wish I could be everywhere at once, because there are so many events involving 3D coming up well worth attending. Unfortunately short of cloning myself, which I don’t think the world is ready for, there’s no way for me to cover everything. So instead, I’ve come up with an alternative plan that I hope will also serve to make this blog more interactive, and encourage an exchange of ideas and information in the 3D space. I’ll list the events here and point out the 3D highlights. If you think you’ll be attending, and have time to contribute a brief review or even just a few comments from whatever event/sessions you attend, please drop me a line.

May 13, Through-Silicon Vias (TSVs): Design and Reliability, Santa Clara, CA
This dinner/presentation, co-sponsored by IEEE Santa Clara Valley CPMT Society Chapter, with Electron Devices Chapter, Reliability Chapter, and Circuits and Systems Chapter features Sergey Savastiouk of ALLVIA, who will address the physical design and reliability issues associated with copper through-silicon vias that have not been fully resolved. I suspect that Savastiouk, considered to be one of the pioneers in TSV and founder of the first TSV foundry, can certainly provide a first-hand perspective of what is yet to be overcome before TSV reaches full market adoption. Harvey Miller of IEEE will guest blog this event. I’m looking forward to reading his review.

May 20 – 22, SEMICON Singapore 2009
Known as the Asian epicentre for test, assembly and packaging, this SEMI-sponsored event has always been the one to focus in the back-end. A review of the symposium line-up turned up two 3D focused presentations; New Packaging Solutions for Wireless: Wafer Level Package 3D Evolution, presented by Xavier Baraton, of ST Microelectronics Pte Ltd; and Approaches and Strategies for TSV, presented by Vish Srinivasan of Applied Materials.

May 27-29, ECTC 2009 – San Diego, CA
In addition to the obvious 3D focused sessions, such as 3D IC integration, TSV, Interconnects for 3D IC integration, and TSV characterization, 3D focused presentations cross over into many of ECTC’s sessions. To name a few, as part of the advanced flip chip packaging session, representatives of STATS ChipPAC will present a paper titled “Three-tier PoP Configuration Utilizing Flip Chip Fan-In PoP Bottom Package”; and as part of the MEMS MEMS, Sensors, and Embedded Packaging Technologies session, representatives of Infineon will present a paper about 3D image sensors using 3D interposers. Even though I plan on attending and covering as much as I can myself, I’d certainly welcome guest blogger contributions for this event.

May 29, 2009 Design Technologies for 3D Integration – CEA-Leti, Grenoble, France
As an extension of their R&D partnership, CEA-Leti and Ecole Polytechnique Fédérale de Lausanne (EPFL), have launched a monthly seminar series for students and professionals to discuss technical issues facing micro- and nanotechnology researchers. This seminar, led by Dr. Vasileios Pavlidis, will take place at Leti, in Grenoble France.

That’s a lot happening for one little month. Since May jumps right into June, and events are happening early, I’ll post June events later this week. – F.v.T

3D from all angles at DATE 2009 3D workshop

As I was unable to attend Design Automation Test in Europe (DATE 2009) myself, but felt the information being shared there would be useful to my readers, I asked fellow 3D enthusiast, Yann Guillou, new technology marketing, St Ericsson, if he would write a guest post for “Françoise in 3D”. He graciously agreed, and what follows is his coverage of the event. -- F.v.T

Overview
Nice, in the French Riviera, hosted a hot event on 3D TSV integration in late April. Indeed, one of the Friday workshops of DATE 2009 was dedicated to 3D integration and brought together experts from design, architecture, process, test, and packaging. More than 70 industrial and academic attendees from Europe, Asia and the US attended. In these difficult economic times, it is a proof of the quality of the papers and speakers. Luckily, I had the opportunity to co-chair the event with organizer Erik Jan Marinissen from IMEC and his colleague Geert Van der Plas.

Keynotes
The workshop started with two talks delivered by invited speakers, followed up by 6 papers selected out of 35 submissions, more than 20 posters. A panel discussion with 3D experts concluded this intense day.

Sitaram Arkalgud from Sematech delivered a keynote address on the promises of TSV, and addressed the main technological challenges. He went through all the process steps and options to achieve 3D structures with TSV. Very clear in his explanations, his presentation enabled the test, design, architecture community of DATE to have a global overview of the TSV technology. He showed some cost simulation done by Sematech and stressed that the applications will drive most of the choices. He concluded by sharing results of a survey done by Sematech listing the main challenges of 3D TSV seen by the companies. And surprisingly for some people, the TSV process did not appear to be the most challenging item. 3D design tools and methodologies, thermal management, supply chain definition or test strategy were among the top ranked. Technology was not. He insisted on the need for a roadmap, and again, a roadmap based on the applications. As of today, most of the TSV roadmaps are technology driven, bottom-up roadmaps. He would recommend a top-down assessment from the system driver. That would help in building coherent 3D R&D and getting the critical mass. He concluded by stating TSV was not a single technology element but part of a whole of domains and competencies.

The second invited speaker, Riko Radojcic from Qualcomm, gave some flavors on Qualcomm CAD strategy for 3D TSV. He insisted on what he calls “Pathfinding,” “TechTuning,” and “Design Authoring.” He underlined the thermo-mechanical challenges related to 3D TSV and the new paradigm coming. Difficulties will come from the multi-scale thermo-mechanical analysis that will be required with 3D structures: mm scale at packaging level, µm at chip level, nm scale at transistor level. He added a 2.5D design environment should be enough at the beginning for stacks of dies up to 2. Then, a real 3D environment will be required.

Presentations
Interests of TSV for different applications were presented by both STMicroelectronics and Toshiba for multimedia and multi-core processors. Endicott Interconnect showed some R&D work on advanced substrates with vertical vias (not TSV in that case!), eventual sufficient solutions for particular applications. Georgia Tech presented test solutions for 3D, whereas IMEC presented some results based on the cost model tool they internally developed.

Panel Discussion
Pol Marchal (IMEC) moderated the final panel discussion. Showing 3D TSV samples done at IMEC, he provocatively asked the panelists: “Look, it is possible to make it; we did stack of die with TSV.” He asked them: “Why not tape out products next year?”

Nicolas SIllon (CEA-LETI) gave an overview of LETI latest developments. He announced it will soon be possible to manufacture product with low-density TSV. LETI will be ready for it. Regarding high-density TSV, he added he was wondering if there were today some applications requiring thousands of TSV with diameter of a few microns only.

Paul Siblerud presented EMC3D latest developments and underlined the most critical process steps to make TSVs. He concluded by saying some challenges were existing but none were seen as a show stopper.

Pascal Urard (STMicroelectronics) presented the first products on the market from STMicroelectronics with TSV, the image sensors. He answered the moderator’s question by saying, yes, we can manufacture products with TSV. They are not 3D at IC level today, but they could be in future.

Geert Van der Plas (IMEC) highlighted that the analog and RF community should be more involved in 3D TSV as many improvements could come from this technology.

Krishnendu Chakrabarty (Duke University) gave some insight on test and explained the nice concept of “pretty good die” for 3D.

Finally, Lisa McIlrath (R3Logic) pointed out the fact that CIS or a stack of DRAM with TSV can be designed "by hand" whereas logic/memory or true heterogeneous cannot.

The panel session finished the day on an optimistic note. Let’s solve all these challenges now!

An Electronic Workshop Digest is available for download at the workshop’s web site
Contact Yann Guillou at Yann.Guillou@stericsson.com

The post-fab process debate for 3D ICs: foundry or OSATS

Inquiring minds want to know: who is going step forward and claim ownership of post-fab processes for 3D IC stacking using through-silicon vias (TSVs)? This has been a topic of debate for some time, with no real solution, although plenty of reasons why one or the other is the way to go, depending on who you talk to. Here's my understanding of the situation.

First of all, there’s a hodge-podge of process flows being tossed around. Some are more suited to a fab environment, and others are more suited to an OSATS environment. Additionally, some approaches are suited to specific applications. For example, CMOS image sensors, the first TSV application in production, uses a via-last approach that requires no adaptation to front-end technologies. However, memory stacks are targeting via-first due to a lower cost-of-ownership.

To grasp it all, it’s important to understand the basic concepts – creating the vias themselves, and stacking the die. The EMC^3D Consortium has developed two proprietary process flows, iTSV and pTSV, both currently based on a die-to-wafer stacking process rather than wafer-to-wafer. iTSV is a via-first approach, in which vias less than 10 microns are formed after CMOS process, but before BEOL processes. Alternatively pTSV is a via-last approach, with vias formed before bonding, but uses the packaging infrastructure.

According to Tom Gregorich, VP of packaging at Qualcomm, there are two process flow options for creating TSV through-silicon stacks (TSV TSS) using a via-first approach. In the die-to-wafer flow, stacking happens during post-fab processing, and the diced die stack is treated as a single die in the assembly processes. In a die-to-substrate flow, the diced top and bottom bumped die arrive at the assembly house independent of each other, and are stacked directly on the substrate medium at assembly house.

In either of these flows, the processes that happen at the foundry end at via formation, and the flows are identical up to the micro-bumping step. Post-fab processes of thinning, dicing, and stacking can occur either at the foundry, the OSAT or a third, yet to be established location. Gregorich says the difference is that die-to-wafer requires post-fab process to be co-located with the OSATS, due to the fragile and expensive die stack, but with die-to -substrate can be independent of each other. “ TSV/TSS requires a significant expansion of and investment in post fab processing operations,” he notes.

So according to Gregorich, the million dollar question is who will make the investment in post-fab processes, the foundries or the OSATS? Thus far, he says the base of technology is already in the OSATS, and Amkor is investing in the TSS processes. But will foundries who invest in TSV processes also invest in the post-fab processes? TSMC just announced it will ready its 300mm facility for TSV processes by June. Will they take the leap and extend that to include post-fab processes for D2W stacks?

If everyone is right, then it doesn’t seem to be a case of either or, but rather, an application-specific issue. As we often see when it comes to this industry, the solutions are never straight forward. In this case, the savviest of fabs and OSATS will see opportunity in the investment, and both options will be available. Meanwhile, those involved in developing processes, equipment and materials are covering all the bases to ensure what they’re developing can suit all the available scenario: via-first or last; W2W or C2W, foundry or OSAT. That’s my take on the situation. I’m curious to know what others think will happen. ( Don’t be shy – that’s what the comment function is meant to be used for.) – F.v.T.

Following the 3D innovation path to profitability

In last week’s email update, I talked about the pendulum starting to swing back the other way, albeit ever so slightly. It’s little things, such as SEMI’s book-to-bill rising from a frightening .48 to a less ominous .61; to bigger things, like TSMC announcing they will invest in R&D despite a hiring freeze in other sectors. As part of it's roadmap to innovate its way out of the slump, the company claims it will have its 300mm fab ready to manufacture TSVs by June. This is exciting news for equipment and material suppliers who have committed to investing in TSV processes.

Whether or not you're a proponent of TSV, it’s clear that companies who are investing in those technologies are faring better these than those who are hacking away at the bottom line to weather the storm. It seems to be working for SUSS MicroTec and EV Group, who have both invested in developing tool sets for wafer bonding, lithography, and mask aligning for the 3D IC integration market. Last week, SUSS announced an order from Nemotek Technologie for multiple lithography systems to be used for manufacturing the company’s CMOS images sensors (CIS). As CIS was the first application to adopt TSV processes in volume production, this win helps establish SUSS as an equipment provider for CIS.

On the heels of that news, came EV Group’s announcement that they will increase production capacity due to “strong order intake” driven by R&D investment in the 3D IC and nanoimprint lithography markets. EV Group strategically established itself in academia, shrewdly anticipating that while capex spending would fall off in the public sector, universities and research institutes would be investing in 3D IC integration to be ready for the rebound.

In his recent SemiSpice blog post, Tom Morrow recounts the different approaches taken by both Kelloggs and Post to survive the Great Depression. Reading it, I thought of Lam Research and Applied Materials (AMAT), equipment vendors who both offer etch tools for 3D IC applications. See if you can guess who is the Post and who is Kelloggs in this scenario. In December 2008, AMAT made headlines with its launch of the Silvia etch tool, then joining EMC^3D and most recently entering into a joint development agreement with Disco to develop wafer thinning processes for TSVs. The only news I’ve seen about Lam in the same time frame is a layoff of 600 employees in November, and another 375 in March. Both layoffs were part of a plan to reduce Lam’s cost structure. In December, Applied announced a cash dividend, while in April, Lam announced a quarterly loss.

While cost cutting may help the bottom line in the short term, it’s my experience that in the long run, innovation and investment goes a lot further to improve a company’s image and ultimately its bottom line, not to mention establish company moral and loyalty. Kudos to the companies and organizations that choose not only to invest and innovate, but also publicize accomplishments. It gives us all something to strive for. -- F.v.T.

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Lisa McIlrath, R3 Logic: design tools for 3D IC are on the way

Mea culpa. I may have jumped to conclusions in yesterday’s post. Although it appears to those developing 3D IC integration processes that the design community hasn’t been heeding the call for the much needed design tools, after talking with Lisa McIlrath of R3 Logic, I realized there’s a lot more to it than that. In fact, the message has been heard, but these things are more convoluted than we think. In fact, it's a bit of a cart-before-the-horse situation. How can design tools be developed until the process technologies, characterization, and paramaters have been determined, and prototypes tested? For that matter, each customer is likely to establish its own design rules.

Consider that 3D IC integration is still a very new field, and that everyone is very much in what McIlrath called “pathfinding mode”; exploring different designs before having the parameters figured out. She said that there’s lots of advance work being done to discover different customer needs. Design tools needed now for CMOS image sensors and soon for stacked memory may not necessarily turn out to be the same ones needed down the road for heterogeneous integration. Unfortunately, it’s still not clear what the winning applications will be.

For large companies, there's not much incentive to invest in development until the picture is clearer and the market is big enough. However the buzz is that Cadence has been some internal development, and and Synopsis and Mentor are sending some of their people to Friday’s 3D Integration Workshop at DATE 2009, in Nice, France. Clearly, the interest is growing.

McIlrath said that although it might be risky and difficult for small companies to set a course on a tool that may not be adopted, it’s also easier for them to be agile as the market shifts and changes. For example, R3 Logic discovered a need by the research community for a layout editor, so they partnered with MicroMagic to develop one. (Tezzaron Semiconductors, pioneers in manufacturing stacked memory with TSVs uses the tool, and has endorsed it.) This week at DATE 2009, McIlrath says R3 Logic will be showcasing a 3D floorplanning tool scheduled for install this summer. Additionally, last month, the company announced a collaboration with ST-Microelectronics and CEA-LETI to develop a full 3D design flow.

McIlrath says that although it’s regrettable that there aren’t more tools out there and available, she doesn’t agree that the lack of design solutions, or test for that matter, is a blocking factor in TSV adoption. “3D integration is going to go ahead with or without any particular player,” she said. “The design tools are coming. Our goal is to find the most appropriate tools to suit the needs of the users.” – F.v.T

DATE 2009 Addresses Design for 3D Integration

It looks as though the call is finally being heard. Those deeply involved in 3D IC Integration using through silicon vias (TSV) as a method of interconnect have been banging these particular drums and sending up smoke signals to the design and test communities for quite some time now with the same message: WE NEED DESIGN SOLUTIONS and WE NEED METHODS FOR TEST.

During the 3D Panel held last month at IMAPS Device Packaging Symposium, panelists and attendees alike speculated about the why’s and wherefores of the logjam for both; but no one could really come up with a concrete answer. While several smaller EDA vendors were acknowledged for having developed tools for 3D IC design (Javelin Design Automation, MicroMagic, and R3 Logic), the question of when “the big guys” (Mentor and Cadence) would jump on board. The collective assumption is that until TSV is closer to market adoption, there’s no real need for the larger design houses to jump into the ring. Test for TSV is still very much an enigma.

Therefore, it was with delight that I reviewed the agenda for Friday’s workshop at DATE 2009, 3D Integration – Technology, Architecture, Design, Automation and Test. Workshop organizers, Yann Gillou, of ST Ericcson, and Erik Jan Marinissen and Geert Van der Plas, both from IMEC; have assembled a line-up for attendees from the design and test communities designed to educate attendees about the critical need for solutions, and to spark interaction between researchers, practitioners, and others interested in 3D IC Integration.

Session 1, moderated by Lisa McIlrath of R3 Logic, kicks off with a keyote addressby Sitaram Arkalgud, of SEMATECH, titled The Promise of Through-Silicon Vias, followed by invited speaker, Riko Radojcic from Qualcomm, who will outline requirements for the design-for-3D environment. The talk will focus on the design environment and EDA tools necessary for what Qualcomm identifies as the ‘Stage 1’ class of products, consisting of a functionally partitioned two-die stack. He will identify three classes of methodologies and associated EDA technologies.

The rest of the day addresses the gamut of issues surrounding design and test, ranging from power integrity issues and bandwidth optimization, to SOC test architecture, test strategies for 3D IC, and much more. In addition to live presentations and 22 poster sessions, the day will conclude with a panel discussion, The Future of 3D Integration From All Angles, moderated by Peter Ramm, of the Fraunhofer Institute. Panelists include Roger Carpenter, Javelin Design Automation; Krishnendu Chakrabarty, Duke University; Paul Siblerud, Semitool; Nicolas Sillon; CEA-LETI; Pascal Urard, ST Microelectronics; and Geert Van der Plas, IMEC.

They may not have the answers yet, but at least they’re getting the message. It’s a start. -- F.v.T

Another 3D supply chain success story

My post about Imbera’s achievements the other day reminded me of another supply chain success story I’ve been meaning to talk about. Last month at IMAPS Global Business Council, Marc Robinson of Vertical Circuits (VCI) shared how the start-up has successfully taken on an industry workhorse, (wire bond for die stacking) with an alternative that with something completely new and also cost-effective. VCI’s core technology is a “virtual via” interconnect that involves jet-dispensing silver filled polymer conformal conductive polymer up the edge of a chip stack to vertically connect bond pads.

Let’s face it, bringing an innovative process into volume production in the semiconductor industry is not a quick or easy task. This is a tough crowd we’re dealing with – very set in their ways. The message is clear – those that succeed the fastest are those that tend to leverage existing infrastructure, because any new process that also requires a new toolset is going to take a while to catch on. (Take IBM’S C4NP for wafer bumping, for example – great concept and an elegant, cost effective process, but required SUSS MicroTec to develop a completely new line of equipment. To date – the only install I’m aware of is at IBM’s facility in Fishkill, NY – please somebody correct me if I’m wrong!)

So how has VCI succeeded where others have been waylaid? According to Robinson, the first time out of the gate wasn’t so successful because they hadn’t taken the power of the existing supply chain seriously. They realized quickly they would have to fit its existing infrastructure conveniently to be adopted. “Until there was a supporting supply chain in place, it fell on doubting ears,” noted Robinson. This meant partnering with supply chain people —equipment and materials suppliers—and subsequently demonstrating how the process reduces the number of steps and the number of machines in the factory so that however the manufacturer looked at it, they would see the advantage. The message to device manufacturers: it’s not going to cost you more to adopt this technology.

So VCI developing partnerships with well-established equipment and materials suppliers such as Asymtek, Lord Corporation, Disco, SCS, and Resonetics, and then approached IDMS and OSATS for commercialization and IP licenses as a group. “We’ve signed a number of licenses now because we addressed them as a team,” noted Robinson. The equipment and material supply chain partners helped to convince customers that the supply chain is ready for adoption of VCI’s technology. Additionally, when they changed to a partnership approach, material and equipment suppliers also benefited, and VCI became successful in its endeavor.

All of these efforts have resulted in a process that has been implemented into micro SD cards. They are reportedly achieving 8 die stacks at 200µm pitch; more than enough for memory in a smaller footprint than wire bond. The company reports that the technology has been licensed to IDMs and OSATS (but can’t say who).

Although success didn’t come overnight – Robinson says he’s been working with this technology for 12 years – it’s still relatively quick in semiconductor years. (Consider that it took flip chip over 40 years to reach high-volume production). The important lesson is that the best way to succeed in this industry is with an “if you can’t beat ‘em, join ‘em” approach. It’s something to think about. – F.v.T