Filled vs. conformal vias: the consensus

Dr. Zhang, I think we have reached a verdict.

Bob Patti wrote in to confirm Anonymous Caller’s statement regarding polymer-filled, copper-lined TSVs, and also provided some additional data to support his comments. I’ve taken the liberty of paraphrasing his comments here:

With the caveat that he is not a “big fan” of conformal vias, and merely providing data, Bob stated:

“Certainly filling vias with a polymer makes sense to keep material from being trapped and depending on what processing may need to follow, it may be required. A via-last interposer might be a better solution. However, Dr. Zhang's question was is it possible to metalize both sides without filling, apparently it is, shown here in this ZyCube presentation (see slides 29-30, the CIS pictured is from Oki.)

At Tezzaron, we only use filled tungsten via first (middle) processes. I don't think copper via-first is a good alternative, except for interposers. Tungsten TSVs are, at best, limited to ~20µm depth, so copper is (at least currently) the only alternative for vias needing to go more than ~20µm deep. So interposers really must use copper. The issue with filled copper at high aspect ratios and/or large diameters is the exposure to thermal cycling. An interposer will not be exposed to numerous 300-400°C temperature cycles, as a copper via-first chip would be. So interposers are far more likely to tolerate filled vias.

Most memories that I am familiar with, other than our own, are via-last copper. I think they are also conformal, but I could be wrong. This makes them look like the Oki sensor."

So in general, the consensus is that as long as the via formation occurs after the metallization layers, as in via last for CIS, or certain interposer applications, a conformal via is fine. Otherwise, the via should be filled with something: copper, tungsten, or polymer. Got it. -- F.v.T.

A final (?) word on filling TSVs

Now look what I’ve started. After posting Bob Patti’s solution for performing UBM with conformal TSVs, I got a phone call from a 25 year industry veteran who prefers not to be identified, but who disagreed with Bob’s response. He maintains that when forming TSVs in a via-first approach for the purpose of silicon interposers, they must be either completely filled with copper, or lined with copper and filled with either a polymer material or solder, because if you attempt to put a redistribution layer or UBM layer on without filling them, “all the junk” will fill the via. He also noted that in the case of via-last formation for CMOS image sensor applications, there is no need to completely fill the via. I forgot to ask him if the same applies with DRAM memory stacks, which is Tezzaron’s area of specialty, so I’m thinking we may not have heard the last of this discussion.

Although a purely coincidental happenstance, yesterday’s debate turns out to be the ideal lead-in for my next announcement. Beginning July 6, and running through July 24th I will be moderating the BrightSpots 3D IC Forum, hosted by MCA Public Relations in cooperation with SemiNeedle, which will enable industry professionals to participate in an active discussion exploring the key issues surrounding 3D ICs from design to manufacture. The online round-table format offers a platform for continuous dialogue that extends the life of a traditional panel event and features a panel of industry experts ready to discuss critical issues associated with 3D IC technology initiated by questions from the public. To join the online discussion or log on to monitor progress, visit www.semineedle.com/MCA3DIC. You can also monitor BrightSpots-related activities on Twitter under the hash tag: #MCA3DIC. I’m very excited to be a part of this event, and look forward to covering it on my blog. – F.v.T.

TSV copper fill: is it necessary for UBM?

In response to a recent post about the whether/when it is necessary to completely fill TSVs, or sufficient to line them, I received an inquiry from Dr. Zhang of IME, where he has been researching with TSV formation for 2 ½ years. According to Zhang, he hasn’t been able to build reliable vias without completely filling them (either with all copper or copper liner + polymer or other materials). He cited an illustration from a paper he co-authored for ECTC 2009, titled Package Development of Through Silicon Via (TSV) Interposer Technology for Large Die (21x21mm) Fine-pitch Cu/low-k FCBGA (proceedings pp. 305-312) which demonstrates that it is necessary to completely fill the vias in order to perform front- and back-side metallization/UBM (under bump metallurgy). The example shown here is performed for a TSV interposer application.

Zhang inquired how it is possible to do front-side and back-side metallization/UBM without filling the vias. As I am an industry journalist and not a research scientist, I decided to pose the question to my readership, both to help Dr. Zhang further his research, and also to help create the atmosphere of interactivity I’m hoping to inspire with this blog.

If any of you can provide an answer to this question, please let me know, and I’ll post the response here. – F.v.T

More about UBM for conformal TSVs

In response to the previous post, Bob Patti of Tezzaron Semiconductors weighed in with a solution to performing under bump metallization (UBM) on conformal (lined rather than filled) TSVs. Patti says that Dr. Zhang is correct in stating that you can't put UBM on top of a conformal TSV. However, he suggests solving the issue by placing a pad next to the TSV and putting the UBM there. Thanks for your help, Bob! - F.v.T.

News from IMEC’s technology forum

From the looks of my inbox, it’s been a busy week at IMEC, between the 25th anniversary celebration and technology forum.(Incidentally, Bill Acito of Cadence provided the words behind the IMEC acronym in response to my last post. According to the link he gave me to Wikipedia, IMEC stands for either Interuniversity Microelectronics Centre, or International Medical Equipment Collaborative. I’m guessing the one the IMEC we’re all familiar with is the first.)

Probably the most significant announcement is the passing of the president and CEO batons from Gilbert Declerck, who has held that position for the past 10 years, to Luc Van den hove, who was been with the organization for his entire career in various roles, most recently as Executive V.P. and Chief Operating Officer. Van den hove says he intends to continue building on the foundation established by Declerck during his tenure, and will continue to develop research partnerships to connect technology and industry, expanding activities in application-oriented research.

Also noteworthy for 3D integration followers is the expanded partnership with TSMC. The Taiwanese semiconductor foundry announced plans to expand its R&D efforts, and has decided to base its European R&D efforts at IMEC. That news, combined with the company’s announcement in April that its 300mm fab will be ready to manufacture TSVs by June, leads me to believe that the gears might start turning towards market adoption.

Other announcements from the technology forum were in the area of photovoltaics research with Schott Solar, brain research, and spectrum sensing capabilities for cognitive radios. Details can be found here on IMEC’s website. – F.v.T

What’s your semi lingo IQ?

I’ve long been fascinated with the vernacular of the semiconductor industry, which is riddled with acronyms that can often mean different things whether you’re referring to front-end or back-end applications. Additionally, as 3D technologies have developed, so has a whole new set of terms that are evolving right along with the processes. It certainly makes for interesting discussion, as I found out last week at ECTC 2009 (that's Electronics Component Technology Conference).

For example, SoP can mean small-outline-package or system-on-package depending on who you talk to, and before SiP referred to a system-in-package, it was a single-inline-package (not to be confused with a DiP, or dual-inline-package). And before a system-in-package was called a SiP, it was referred to as a MCM, or multichip module. Confused yet? Jeanne Beacham, of Delphon, and I started joking in the buffet line at the conference. “What’s so great about PoP,” quipped Jeanne Beacham of Delphon. “What about MoM?” I laughed, but then again, it’s entirely possible. PoPs made of multichip packages could be called multichip-on-multichip (MoM). They certainly will be able to do lots more than a PoP (I’ll just leave it at that).

What’s more, we toss around terms like FEOL and BEOL (front-end-of-line and back-end-of-line) and FOUP (front opening unified pod) like everyone knows what we’re talking about. (I actually had to look that one up while writing this. I know what FOUPS are; those orange thingies that hold the wafers before and after processing. I just didn’t know what the letters stood for.)

All kidding aside, settling on a set of terms for 3D processes is actually the first step to standardization, notes Eric Beyne, of IMEC. We were discussing how chip and die are used interchangeably, (specifically in reference to die-to-wafer stacking or chip-to-wafer stacking.) and the confusion it causes for those who distinguish between the die and the chip based on whether it’s bare or packaged. Last year, we were told via first could be further distinguished into via-early (before CMOS) or via-middle (after CMOS but before BEOL). Oh great, there’s another one. (For those about to ask, CMOS stands for complementary metal oxide semiconductor. No wonder we don’t usually write that out.) In any case, Beyne says the ITRS (International Technology Roadmap for Semiconductors) is working to standardize definitions, because classification of technologies is required to define a roadmap.

Incidentally, if someone can tell me what IMEC stands for, the drinks are on me. – F.v.T.

TSVs: just the tip of the 3D ICeberg

At ECTC last week, I counted at least 21 presentations dedicated to TSVs alone, and 13 dedicated to other processes for 3D IC integration. The sheer volume and depth of research required around bringing these technologies to market is sometimes lost on those of us who sit outside the circle of academia and research, and only hear about those that make it to marketability. And although TSVs have become the poster child for 3D IC integration, sometimes we forget that there are other steps of equal importance to achieving these 3D stacks; namely backgrinding, thinning and dicing; temporary bonding and debonding for both wafer-to-wafer (W2W) chip-to-wafer processes (C2W); and chip stacking.

According to IMEC’s Eric Beyne, while many companies are involved in developing materials and equipment for TSV processes (etch, seed layer, fill, etc.) there are only 2 equipment manufacturers (EV Group and SUSS MicroTec) that offer tools for temporary bonding and debonding processes, and only a few materials companies (Brewer Science, 3M, and Dupont) developing temporary bonding materials. Beyne described one temporary bonding material that when heated, allows the device wafer to slide apart from the carrier wafer; and another that vaporizes the material holding them together. Unfortunately, both of these materials involves high temperatures, which, when used in sequential processes to achieve multiple chip stacks, can stress the ultrathin device wafers. Therefore, IMEC is working on a parallel process to overcome address this. One approach is to stack the chips using a sort of stencil to maintain alignment, and then perform the bond step all at once.

Chip stacking is another step still requiring some solutions in C2W processes, where the perfect combination of speed and accuracy is yet to be achieved. S.E.T has developed a high-precision, flexible die bonder that reportedly achieves a throughput of 150pph, earning the company installs at IMEC, SEMATECH and CEA-Leti; but according to Mike Thompson, CTO of Replisaurus, S.E.T’s parent company, that number needs another zero (1500) to make it volume-production-capable. Solving this alignment plus throughput conundrum is the focus of TNO’s Bluebird project with Datacon. As part of the EMC3D consortium, EV Group is also working with Datacon to solve the C2W stacking issue.

What’s not being revealed is likely to be more important than what is being revealed. As was pointed out to me on more than one occasion last week, companies aren’t likely to talk about what they’re working on until it’s a done deal. And they never talk about what they’ve tried that has failed, which could ultimately be as useful for competitors to know about as the successes are. In any case, it appears that there’s still work to do before all the stars align. – F.v.T.