Lisa McIlrath, R3 Logic: design tools for 3D IC are on the way

Mea culpa. I may have jumped to conclusions in yesterday’s post. Although it appears to those developing 3D IC integration processes that the design community hasn’t been heeding the call for the much needed design tools, after talking with Lisa McIlrath of R3 Logic, I realized there’s a lot more to it than that. In fact, the message has been heard, but these things are more convoluted than we think. In fact, it's a bit of a cart-before-the-horse situation. How can design tools be developed until the process technologies, characterization, and paramaters have been determined, and prototypes tested? For that matter, each customer is likely to establish its own design rules.

Consider that 3D IC integration is still a very new field, and that everyone is very much in what McIlrath called “pathfinding mode”; exploring different designs before having the parameters figured out. She said that there’s lots of advance work being done to discover different customer needs. Design tools needed now for CMOS image sensors and soon for stacked memory may not necessarily turn out to be the same ones needed down the road for heterogeneous integration. Unfortunately, it’s still not clear what the winning applications will be.

For large companies, there's not much incentive to invest in development until the picture is clearer and the market is big enough. However the buzz is that Cadence has been some internal development, and and Synopsis and Mentor are sending some of their people to Friday’s 3D Integration Workshop at DATE 2009, in Nice, France. Clearly, the interest is growing.

McIlrath said that although it might be risky and difficult for small companies to set a course on a tool that may not be adopted, it’s also easier for them to be agile as the market shifts and changes. For example, R3 Logic discovered a need by the research community for a layout editor, so they partnered with MicroMagic to develop one. (Tezzaron Semiconductors, pioneers in manufacturing stacked memory with TSVs uses the tool, and has endorsed it.) This week at DATE 2009, McIlrath says R3 Logic will be showcasing a 3D floorplanning tool scheduled for install this summer. Additionally, last month, the company announced a collaboration with ST-Microelectronics and CEA-LETI to develop a full 3D design flow.

McIlrath says that although it’s regrettable that there aren’t more tools out there and available, she doesn’t agree that the lack of design solutions, or test for that matter, is a blocking factor in TSV adoption. “3D integration is going to go ahead with or without any particular player,” she said. “The design tools are coming. Our goal is to find the most appropriate tools to suit the needs of the users.” – F.v.T

DATE 2009 Addresses Design for 3D Integration

It looks as though the call is finally being heard. Those deeply involved in 3D IC Integration using through silicon vias (TSV) as a method of interconnect have been banging these particular drums and sending up smoke signals to the design and test communities for quite some time now with the same message: WE NEED DESIGN SOLUTIONS and WE NEED METHODS FOR TEST.

During the 3D Panel held last month at IMAPS Device Packaging Symposium, panelists and attendees alike speculated about the why’s and wherefores of the logjam for both; but no one could really come up with a concrete answer. While several smaller EDA vendors were acknowledged for having developed tools for 3D IC design (Javelin Design Automation, MicroMagic, and R3 Logic), the question of when “the big guys” (Mentor and Cadence) would jump on board. The collective assumption is that until TSV is closer to market adoption, there’s no real need for the larger design houses to jump into the ring. Test for TSV is still very much an enigma.

Therefore, it was with delight that I reviewed the agenda for Friday’s workshop at DATE 2009, 3D Integration – Technology, Architecture, Design, Automation and Test. Workshop organizers, Yann Gillou, of ST Ericcson, and Erik Jan Marinissen and Geert Van der Plas, both from IMEC; have assembled a line-up for attendees from the design and test communities designed to educate attendees about the critical need for solutions, and to spark interaction between researchers, practitioners, and others interested in 3D IC Integration.

Session 1, moderated by Lisa McIlrath of R3 Logic, kicks off with a keyote addressby Sitaram Arkalgud, of SEMATECH, titled The Promise of Through-Silicon Vias, followed by invited speaker, Riko Radojcic from Qualcomm, who will outline requirements for the design-for-3D environment. The talk will focus on the design environment and EDA tools necessary for what Qualcomm identifies as the ‘Stage 1’ class of products, consisting of a functionally partitioned two-die stack. He will identify three classes of methodologies and associated EDA technologies.

The rest of the day addresses the gamut of issues surrounding design and test, ranging from power integrity issues and bandwidth optimization, to SOC test architecture, test strategies for 3D IC, and much more. In addition to live presentations and 22 poster sessions, the day will conclude with a panel discussion, The Future of 3D Integration From All Angles, moderated by Peter Ramm, of the Fraunhofer Institute. Panelists include Roger Carpenter, Javelin Design Automation; Krishnendu Chakrabarty, Duke University; Paul Siblerud, Semitool; Nicolas Sillon; CEA-LETI; Pascal Urard, ST Microelectronics; and Geert Van der Plas, IMEC.

They may not have the answers yet, but at least they’re getting the message. It’s a start. -- F.v.T

Another 3D supply chain success story

My post about Imbera’s achievements the other day reminded me of another supply chain success story I’ve been meaning to talk about. Last month at IMAPS Global Business Council, Marc Robinson of Vertical Circuits (VCI) shared how the start-up has successfully taken on an industry workhorse, (wire bond for die stacking) with an alternative that with something completely new and also cost-effective. VCI’s core technology is a “virtual via” interconnect that involves jet-dispensing silver filled polymer conformal conductive polymer up the edge of a chip stack to vertically connect bond pads.

Let’s face it, bringing an innovative process into volume production in the semiconductor industry is not a quick or easy task. This is a tough crowd we’re dealing with – very set in their ways. The message is clear – those that succeed the fastest are those that tend to leverage existing infrastructure, because any new process that also requires a new toolset is going to take a while to catch on. (Take IBM’S C4NP for wafer bumping, for example – great concept and an elegant, cost effective process, but required SUSS MicroTec to develop a completely new line of equipment. To date – the only install I’m aware of is at IBM’s facility in Fishkill, NY – please somebody correct me if I’m wrong!)

So how has VCI succeeded where others have been waylaid? According to Robinson, the first time out of the gate wasn’t so successful because they hadn’t taken the power of the existing supply chain seriously. They realized quickly they would have to fit its existing infrastructure conveniently to be adopted. “Until there was a supporting supply chain in place, it fell on doubting ears,” noted Robinson. This meant partnering with supply chain people —equipment and materials suppliers—and subsequently demonstrating how the process reduces the number of steps and the number of machines in the factory so that however the manufacturer looked at it, they would see the advantage. The message to device manufacturers: it’s not going to cost you more to adopt this technology.

So VCI developing partnerships with well-established equipment and materials suppliers such as Asymtek, Lord Corporation, Disco, SCS, and Resonetics, and then approached IDMS and OSATS for commercialization and IP licenses as a group. “We’ve signed a number of licenses now because we addressed them as a team,” noted Robinson. The equipment and material supply chain partners helped to convince customers that the supply chain is ready for adoption of VCI’s technology. Additionally, when they changed to a partnership approach, material and equipment suppliers also benefited, and VCI became successful in its endeavor.

All of these efforts have resulted in a process that has been implemented into micro SD cards. They are reportedly achieving 8 die stacks at 200µm pitch; more than enough for memory in a smaller footprint than wire bond. The company reports that the technology has been licensed to IDMs and OSATS (but can’t say who).

Although success didn’t come overnight – Robinson says he’s been working with this technology for 12 years – it’s still relatively quick in semiconductor years. (Consider that it took flip chip over 40 years to reach high-volume production). The important lesson is that the best way to succeed in this industry is with an “if you can’t beat ‘em, join ‘em” approach. It’s something to think about. – F.v.T

Imbera takes on 3D packaging supply chain issues

While 3D IC integration folks are still scratching their heads trying to determine who will take on post-fab processes, over in the 3D packaging world Imbera has taken ownership of the supply chain issues facing the OSATS-to-PCB assembly end of the line for embedded active and passive technologies.

But let’s back up a bit. It’s well known that 3D configurations have existed in the packaging space for quite some time. In fact, package-on-package (PoP) options from the likes of Amkor, STATS ChipPAC, and ASE are already in volume production. Additionally, various embedded technologies such as the Fraunhofer’s chip-in-polymer (CiP), GE’s solderless “chips first” approach, IMEC’s ultra-thin chip package (UTCP), and Imbera’s integrated module board (IMB) technology all offer viable 3D technology solutions, at least in theory. Unfortunately, manufacturing these embedded 3D packages falls into that elusive “no-man’s-land” between OSATS and EMS providers, and therefore have been stalled at the “who’s-going-to-do-it” phase. (see: Executive Panel Addresses Options in WLP)

Luckily, thanks to USD $15M in series B funding from NorthZone Ventures, Index Ventures and Conor Venture Partners, Imbera is now positioned to do something about those pesky supply chain issues.

Risto Tuominen, CTO of Imbera, talked to me about the how the company intends to put the money to use. “There are lots of embedded technologies in development,” notes Tuominen, “but nobody is able to offer a full turnkey solution for an embedded technology supply chain.” Imbera’s intention is to merge packaging and PCB processes into one entity, beginning with a new high-volume manufacturing operation in Sangsong-ri, South Korea.

Although Japanese PCB manufacturer Ibiden licensed IMB technology in July 2008, Tuominen says the company’s focus over the last year has been to create its own manufacturing solutions. The goal is for the customers to provide the known-good die (KDG) and Imbera outputs the completed device - whether it is a QFN, BGA, system-in-package (SiP), or system-in-board (SIB).



The latest milestone was a joint venture (iDD) completed with Korean PCB manufacturer Daeduck in Q3 2008. “Daeduck offers a whole PCB infrastructure with proven capabilities in substrate and motherboard manufacturing.” He explained, “There’s a whole technology portfolio we can utilize.” It sure makes more sense than buying a PCB manufacturer. As part of the iDD joint venture, the new facility (owned 60% by Imbera and 40% by Daeduck) will be outfitted with new equipment.

The biggest question was how they managed to get funding now, given the current state of the industry and economy? For the past few years, Imbera has focused on developing a new business model, which included acquiring a new capital owner base in 2007; appointing a new CEO acquired in late 2007; and relaunching Imbera in early 2008, based on the new model. “We’re very fortunate to have the investors that we have,” said Tuominen, “We didn’t have to change a thing.”

That said, Tuominen was happy to share the secrets of Imbera’s success. He said it’s important to show a roadmap with technology improvements going forward, and that the benefits needed to be apparent from the outset. Everything must be of the highest quality, and that the customer can use it without changing existing infrastructure or design tools. “In the end, the technology needs to provide an efficient manufacturing solution,” he noted, “and you need to be able to show a cost reduction.”

But most importantly, rather than passing the buck, Imbera is taking ownership of the OSAT/PCB assembly bottleneck. Let’s hope other sectors of the 3D market find inspiration in this company’s achievements. – F.v.T

EVG’s partnership with Léti adds a third dimension

As the old saying goes, things usually happen in threes… and in this case 3D. Three years ago, EV Group (EVG) teamed up with Brewer Science, Inc. (BSI) to develop temporary wafer bonding and debonding processes using EVG tools and BSI's materials. Just a few weeks ago, CEA Léti and BSI announced a joint development program (JDP) for temporary wafer bonding and debonding processes to achieve 3D IC integration using TSVs. Last week, EV Group made a similar announcement regarding a JDP with Leti. Just as I suspected, this move completes a 3-way collaboration for accelerating 3D IC integration. I spoke with Nicolas Sillon, head of the laboratory for advanced packaging and 3D integration at Leti; and Stefan Pargfrieder, EVG's business development manager, to get some more details on the arrangement.

According to Sillon, the program with EVG is complementary to what Leti is already working on with BSI. “We’re mixing three competencies: EVG tools, BSI science, and Leti integration schemes,” he said. Pargfrieder concurred, adding that EVG's previous work with BSI developing temporary bonding and debonding processes on their tools proved the best performance using BSI materials. “To have Léti as an industrial R&D partner allows us to make this a mature qualified technology for a broader range of customers.” he added.

In particular, Sillon said that developing 300mm 3D integration wafer processes is the main goal of the program with EVG. From EVG’s perspective, Pargfrieder says the goal is to establish EVG's technology in the market, and learn from partners about tool performance at the early stages of development to better serve the customer. Therefore, the ability to accomplish this using Léti’s research facilities is a benefit.

As all three entities – Léti, BSI, and EVG – are members of the EMC^3D Consortium, I was curious if this work also tied into that organization. According to both Sillon and Pargfrieder, information will be shared only in as much as can be made public. Sillon says the JDP with both EVG and BSI allows Leti to go deeper into development than they can with EMC^3D . Pargfrieder added that some of the information might be useful to EMC^3D, while some must remain confidential for customer projects.

To learn more about this triad’s work, be sure to catch their presentation on at ECTC 2009, which takes place May 27-29 in San Diego, CA. The topic discussed will be Leti’s via-last application on thin wafers using BSI’s science on EVG’s tool. It looks like the power of 3 is catching on in more ways than one. – F.v.T.

"Francoise in 3D" resurfaces in Mesa, AZ

For the past two weeks, I’ve been slightly preoccupied with relocating from Massachusetts to Mesa, AZ. For much of that time, due to the drive across country and then subsequent delay in installing internet access at my new abode, I was disconnected from the internet and industry activities; needless to say, it’s a slightly unsettling feeling for an industry commentator. Today, FINALLY, I’m up and running once more, and catching up on news. It’s not surprising that while I’ve been on hiatus, organizations and companies devoted to developing 3D technologies have continued to make headlines. Let’s start out by recapping some of the highlights:

Just before I hit the road, Harvey Miller of IEEE contacted me about an upcoming event co-sponsored by IEEE Santa Clara Valley CPMT Society Chapter, and Electron Devices Chapter and Circuits and Systems Chapter titled “Through-Silicon Vias (TSVs): Design and Reliability" Sergey Savastiouk, ALLVIA, Inc. being held May 13, 2009 at the Biltmore Hotel in Santa Clara, CA. Savastiouk is a pioneer in TSV, and is responsible for coining the term itself. His expertise, therefore, encompasses the lifespan of this still emerging technology. With that deep a legacy, it should be iteresting to hear what he has to say about the design and reliability issues that have been identified as critical to market adoption.

Despite the state of the semiconductor industry as a whole, there continues to be optimistic news of growth coming out of the R&D sector, especially with regards to developments in 3D technologies. IMEC announced a 2,800m² addition to its research facilities, to expand its research on, among other things, biomedical electronics. IMEC’s most recent 3D contribution in this area is the ultra-thin chip package. EV Group sold a photoresist developer,the EVG101D, to the University of Tokyo, continuing their success in the academic realm.

Collaboration continues to be the name of the game these days, with more announcements almost daily, such as Applied Materials and DISCO joining forces to jump on the wafer thinning bandwagon for TSV processes. Additionally, EVG and CEA Leti have entered into a joint development program involving EVG’s 300mm temporary bonding and debonding technologies. I’m curious to find out more about the connection between this and Leti’s JDP with Brewer Science. Look for more on the topic later this week.

Are the big design tool houses starting to pay more attention to design for 3D ICs? Phil Garrou’s coverage of an IEEE Components Packaging and Manufacturing Technology (CPMT) workshop in Austin, Texas alludes to Cadence’s involvement in that area. What I’m curious to find out is whether they’re referring to design for stacks interconnnected with wire bond or flip chip, or if they’ve addressed design for TSV integration yet.

So many questions yet to be answered! Count on me to find some answers. – F.v.T.

Léti and Brewer Science: sharing a common lab and a common goal

With the recent announcement of CEA-Léti and Brewer Science's agreement to create a common lab for further development of 3D stacking processes using Léti’s thin wafer handling processes and Brewer Science, Inc. (BSI) WaferBOND™ materials, I realized although both names popped up frequently in relation to the EMC^3D Consortium, they tend to keep a low profile. An interview was definitely in order to learn more about the roles they play in 3D IC integration developments. Fortunately Andre Rouzaud and Nicolas Sillon of Léti, and Rama Puligadda and Mark Privett of BSI, were available to answer my questions and provide more in-depth information about the collaboration. Here’s what I learned from them.

Léti’s research field in 3D integration is driven by the needs for increasing the density of functions, with an ultimate goal of heterogeneous integration of functions such as RF, logic, memory, MEMS, using a variety of technologies to achieve these processes at a lower cost. Léti develops methods to use short vertical interconnects between stacked dies, specifically involving TSVs. Since a broad spectrum of options must be investigated, it makes sense to form alliances and consortia to help accelerate commercialization of technology.

“The partnership collaborative model we have at Léti is quite special,” explained Rouzaud. “Although open to multi-partner projects (mainly for upstream research), we promote bilateral collaborations with specific identified partners on determined research domains.” Leti’s involvement with EMC3D is an example of a multi-partner project, while the partnership with BSI (also a member of EMC3D) is an example of a bilateral collaboration. In the case of the latter, part of the program involves the establishment of a mid-term common laboratory where a dedicated Léti team works closely with partner assignees (in this case, BSI) in the Léti premises on commonly defined programs that are periodically assessed, adapted, and adjusted through regular Léti/partner steering committees. This flexibility in the common project evolution allows the partner to take into account possible changes in his market environment or in his business strategy.

In the area of temporary bonding and protective materials, Léti is clearly committed with BSI. While the scope of work being done by Leti and BSI goes beyond their affiliation with EMC3D, extending into specific customer projects, Privett noted that information is shared as it relates to the EMC3D goal of developing TSV process at a cost of <$150/wafer. Leti and BSI’s focus in the common lab agreement is in developing standard processes for TSVs. Specifically, they have been working in the area of temporary bonding and protective materials for handling thin wafers. Process development is geared toward either via first or last, die to wafer (D2W) or wafer to wafer (W2W), in the foundry or in the packaging house. Rama says the goal is to be prepared for all scenarios. Although the processes might require slight adaptation, ultimately they can be done either place. “The partner will choose the solution,” she explained. “Temporary bonding and debonding can be used for both chip to wafer and wafer to wafer processes. The silicon still has to go through back grinding and subsequent post-fab processes for either.”

“We feel via last will be adopted before via first, because the first demonstrations with CMOS image sensors have been done with via last, and no adjustments have to be made to front end processes to achieve that.” noted Sillon.

Although the initial common lab agreement between Léti and BSI is set for 3 years, the flexibility of the arrangement allows for it to change as the project evolves. “We are focused together on the roadmap of 3D integration,” noted Rouzaud. “I suspect it will not be done in 3 years.” Privett added that market research(Yole Développment) points to 3D IC integration being in high volume manufacturing by 2015, at which point only 20% of all memory will be manufactured this way (51% wire bonded, 30% discrete). He said that leaves 80% worth of memory still to be addressed. “Hopefully we’ll still be talking about 3D integration in 3 years,” he said. In the mean time, notes Puligadda, “It’s been a wonderful relationship.” – F.v.T.