Imbera takes on 3D packaging supply chain issues

While 3D IC integration folks are still scratching their heads trying to determine who will take on post-fab processes, over in the 3D packaging world Imbera has taken ownership of the supply chain issues facing the OSATS-to-PCB assembly end of the line for embedded active and passive technologies.

But let’s back up a bit. It’s well known that 3D configurations have existed in the packaging space for quite some time. In fact, package-on-package (PoP) options from the likes of Amkor, STATS ChipPAC, and ASE are already in volume production. Additionally, various embedded technologies such as the Fraunhofer’s chip-in-polymer (CiP), GE’s solderless “chips first” approach, IMEC’s ultra-thin chip package (UTCP), and Imbera’s integrated module board (IMB) technology all offer viable 3D technology solutions, at least in theory. Unfortunately, manufacturing these embedded 3D packages falls into that elusive “no-man’s-land” between OSATS and EMS providers, and therefore have been stalled at the “who’s-going-to-do-it” phase. (see: Executive Panel Addresses Options in WLP)

Luckily, thanks to USD $15M in series B funding from NorthZone Ventures, Index Ventures and Conor Venture Partners, Imbera is now positioned to do something about those pesky supply chain issues.

Risto Tuominen, CTO of Imbera, talked to me about the how the company intends to put the money to use. “There are lots of embedded technologies in development,” notes Tuominen, “but nobody is able to offer a full turnkey solution for an embedded technology supply chain.” Imbera’s intention is to merge packaging and PCB processes into one entity, beginning with a new high-volume manufacturing operation in Sangsong-ri, South Korea.

Although Japanese PCB manufacturer Ibiden licensed IMB technology in July 2008, Tuominen says the company’s focus over the last year has been to create its own manufacturing solutions. The goal is for the customers to provide the known-good die (KDG) and Imbera outputs the completed device - whether it is a QFN, BGA, system-in-package (SiP), or system-in-board (SIB).



The latest milestone was a joint venture (iDD) completed with Korean PCB manufacturer Daeduck in Q3 2008. “Daeduck offers a whole PCB infrastructure with proven capabilities in substrate and motherboard manufacturing.” He explained, “There’s a whole technology portfolio we can utilize.” It sure makes more sense than buying a PCB manufacturer. As part of the iDD joint venture, the new facility (owned 60% by Imbera and 40% by Daeduck) will be outfitted with new equipment.

The biggest question was how they managed to get funding now, given the current state of the industry and economy? For the past few years, Imbera has focused on developing a new business model, which included acquiring a new capital owner base in 2007; appointing a new CEO acquired in late 2007; and relaunching Imbera in early 2008, based on the new model. “We’re very fortunate to have the investors that we have,” said Tuominen, “We didn’t have to change a thing.”

That said, Tuominen was happy to share the secrets of Imbera’s success. He said it’s important to show a roadmap with technology improvements going forward, and that the benefits needed to be apparent from the outset. Everything must be of the highest quality, and that the customer can use it without changing existing infrastructure or design tools. “In the end, the technology needs to provide an efficient manufacturing solution,” he noted, “and you need to be able to show a cost reduction.”

But most importantly, rather than passing the buck, Imbera is taking ownership of the OSAT/PCB assembly bottleneck. Let’s hope other sectors of the 3D market find inspiration in this company’s achievements. – F.v.T

EVG’s partnership with Léti adds a third dimension

As the old saying goes, things usually happen in threes… and in this case 3D. Three years ago, EV Group (EVG) teamed up with Brewer Science, Inc. (BSI) to develop temporary wafer bonding and debonding processes using EVG tools and BSI's materials. Just a few weeks ago, CEA Léti and BSI announced a joint development program (JDP) for temporary wafer bonding and debonding processes to achieve 3D IC integration using TSVs. Last week, EV Group made a similar announcement regarding a JDP with Leti. Just as I suspected, this move completes a 3-way collaboration for accelerating 3D IC integration. I spoke with Nicolas Sillon, head of the laboratory for advanced packaging and 3D integration at Leti; and Stefan Pargfrieder, EVG's business development manager, to get some more details on the arrangement.

According to Sillon, the program with EVG is complementary to what Leti is already working on with BSI. “We’re mixing three competencies: EVG tools, BSI science, and Leti integration schemes,” he said. Pargfrieder concurred, adding that EVG's previous work with BSI developing temporary bonding and debonding processes on their tools proved the best performance using BSI materials. “To have Léti as an industrial R&D partner allows us to make this a mature qualified technology for a broader range of customers.” he added.

In particular, Sillon said that developing 300mm 3D integration wafer processes is the main goal of the program with EVG. From EVG’s perspective, Pargfrieder says the goal is to establish EVG's technology in the market, and learn from partners about tool performance at the early stages of development to better serve the customer. Therefore, the ability to accomplish this using Léti’s research facilities is a benefit.

As all three entities – Léti, BSI, and EVG – are members of the EMC^3D Consortium, I was curious if this work also tied into that organization. According to both Sillon and Pargfrieder, information will be shared only in as much as can be made public. Sillon says the JDP with both EVG and BSI allows Leti to go deeper into development than they can with EMC^3D . Pargfrieder added that some of the information might be useful to EMC^3D, while some must remain confidential for customer projects.

To learn more about this triad’s work, be sure to catch their presentation on at ECTC 2009, which takes place May 27-29 in San Diego, CA. The topic discussed will be Leti’s via-last application on thin wafers using BSI’s science on EVG’s tool. It looks like the power of 3 is catching on in more ways than one. – F.v.T.

"Francoise in 3D" resurfaces in Mesa, AZ

For the past two weeks, I’ve been slightly preoccupied with relocating from Massachusetts to Mesa, AZ. For much of that time, due to the drive across country and then subsequent delay in installing internet access at my new abode, I was disconnected from the internet and industry activities; needless to say, it’s a slightly unsettling feeling for an industry commentator. Today, FINALLY, I’m up and running once more, and catching up on news. It’s not surprising that while I’ve been on hiatus, organizations and companies devoted to developing 3D technologies have continued to make headlines. Let’s start out by recapping some of the highlights:

Just before I hit the road, Harvey Miller of IEEE contacted me about an upcoming event co-sponsored by IEEE Santa Clara Valley CPMT Society Chapter, and Electron Devices Chapter and Circuits and Systems Chapter titled “Through-Silicon Vias (TSVs): Design and Reliability" Sergey Savastiouk, ALLVIA, Inc. being held May 13, 2009 at the Biltmore Hotel in Santa Clara, CA. Savastiouk is a pioneer in TSV, and is responsible for coining the term itself. His expertise, therefore, encompasses the lifespan of this still emerging technology. With that deep a legacy, it should be iteresting to hear what he has to say about the design and reliability issues that have been identified as critical to market adoption.

Despite the state of the semiconductor industry as a whole, there continues to be optimistic news of growth coming out of the R&D sector, especially with regards to developments in 3D technologies. IMEC announced a 2,800m² addition to its research facilities, to expand its research on, among other things, biomedical electronics. IMEC’s most recent 3D contribution in this area is the ultra-thin chip package. EV Group sold a photoresist developer,the EVG101D, to the University of Tokyo, continuing their success in the academic realm.

Collaboration continues to be the name of the game these days, with more announcements almost daily, such as Applied Materials and DISCO joining forces to jump on the wafer thinning bandwagon for TSV processes. Additionally, EVG and CEA Leti have entered into a joint development program involving EVG’s 300mm temporary bonding and debonding technologies. I’m curious to find out more about the connection between this and Leti’s JDP with Brewer Science. Look for more on the topic later this week.

Are the big design tool houses starting to pay more attention to design for 3D ICs? Phil Garrou’s coverage of an IEEE Components Packaging and Manufacturing Technology (CPMT) workshop in Austin, Texas alludes to Cadence’s involvement in that area. What I’m curious to find out is whether they’re referring to design for stacks interconnnected with wire bond or flip chip, or if they’ve addressed design for TSV integration yet.

So many questions yet to be answered! Count on me to find some answers. – F.v.T.

Léti and Brewer Science: sharing a common lab and a common goal

With the recent announcement of CEA-Léti and Brewer Science's agreement to create a common lab for further development of 3D stacking processes using Léti’s thin wafer handling processes and Brewer Science, Inc. (BSI) WaferBOND™ materials, I realized although both names popped up frequently in relation to the EMC^3D Consortium, they tend to keep a low profile. An interview was definitely in order to learn more about the roles they play in 3D IC integration developments. Fortunately Andre Rouzaud and Nicolas Sillon of Léti, and Rama Puligadda and Mark Privett of BSI, were available to answer my questions and provide more in-depth information about the collaboration. Here’s what I learned from them.

Léti’s research field in 3D integration is driven by the needs for increasing the density of functions, with an ultimate goal of heterogeneous integration of functions such as RF, logic, memory, MEMS, using a variety of technologies to achieve these processes at a lower cost. Léti develops methods to use short vertical interconnects between stacked dies, specifically involving TSVs. Since a broad spectrum of options must be investigated, it makes sense to form alliances and consortia to help accelerate commercialization of technology.

“The partnership collaborative model we have at Léti is quite special,” explained Rouzaud. “Although open to multi-partner projects (mainly for upstream research), we promote bilateral collaborations with specific identified partners on determined research domains.” Leti’s involvement with EMC3D is an example of a multi-partner project, while the partnership with BSI (also a member of EMC3D) is an example of a bilateral collaboration. In the case of the latter, part of the program involves the establishment of a mid-term common laboratory where a dedicated Léti team works closely with partner assignees (in this case, BSI) in the Léti premises on commonly defined programs that are periodically assessed, adapted, and adjusted through regular Léti/partner steering committees. This flexibility in the common project evolution allows the partner to take into account possible changes in his market environment or in his business strategy.

In the area of temporary bonding and protective materials, Léti is clearly committed with BSI. While the scope of work being done by Leti and BSI goes beyond their affiliation with EMC3D, extending into specific customer projects, Privett noted that information is shared as it relates to the EMC3D goal of developing TSV process at a cost of <$150/wafer. Leti and BSI’s focus in the common lab agreement is in developing standard processes for TSVs. Specifically, they have been working in the area of temporary bonding and protective materials for handling thin wafers. Process development is geared toward either via first or last, die to wafer (D2W) or wafer to wafer (W2W), in the foundry or in the packaging house. Rama says the goal is to be prepared for all scenarios. Although the processes might require slight adaptation, ultimately they can be done either place. “The partner will choose the solution,” she explained. “Temporary bonding and debonding can be used for both chip to wafer and wafer to wafer processes. The silicon still has to go through back grinding and subsequent post-fab processes for either.”

“We feel via last will be adopted before via first, because the first demonstrations with CMOS image sensors have been done with via last, and no adjustments have to be made to front end processes to achieve that.” noted Sillon.

Although the initial common lab agreement between Léti and BSI is set for 3 years, the flexibility of the arrangement allows for it to change as the project evolves. “We are focused together on the roadmap of 3D integration,” noted Rouzaud. “I suspect it will not be done in 3 years.” Privett added that market research(Yole Développment) points to 3D IC integration being in high volume manufacturing by 2015, at which point only 20% of all memory will be manufactured this way (51% wire bonded, 30% discrete). He said that leaves 80% worth of memory still to be addressed. “Hopefully we’ll still be talking about 3D integration in 3 years,” he said. In the mean time, notes Puligadda, “It’s been a wonderful relationship.” – F.v.T.

Notes from the Exhibition Hall

I have to admit that this year at IMAPS Device Packaging Conference, I spent more time attending technical sessions and less time with the exhibitors than I usually do at an industry event. However, I did manage to check in with a few of them to see what their latest contributions are to the 3D IC and 3D Packaging realm.

Palomar Technologies
I wasn’t surprised to run into Bradley Benton at the Palomar booth – I pretty much expect to see him at these events. In fact, he gave me my first comprehensive lesson in the history of wire bond technologies. I was, however, surprised to learn that the company, which is firmly established in the wire bond business, is venturing into the TSV space with its 6500 Eutectic Die Attach System. Benton says the tool is designed to perform die to wafer processes, and achieves 1.5 µm placement accuracies.

“We recognize that TSV is coming,” he noted. “We have some TSV capabilities now. We’re looking into ways of enhancing that.” Benton says his interest in 3D packaging is why he got into this business 26 years ago. “I always assumed microelectronics would build up and not out.” He said. “What’s new is that we’re finally going at it and doing it with silicon.

SUSS MicroTec
I caught up with Kathy Cook of SUSS MicroTec at the tail end of the poster sessions on Thursday, where she was presenting a poster based on Margarete Zoberbier’s recent presentation at SEMICON Korea about some of SUSS’ equipment technologies for TSVs. Cook explained that polymers adhesives may be necessary for permanent bonding when copper alone isn’t enough to hold the wafers together. The take-away message was the company’s achievement of submicron post bond alignment accuracy (.35µm) for permanent bonding and several other new capabilities involving SUSS’s latest 300mm tools – ACS300 Gen 2 Coater and the MA300 mask aligner. The 300mm permanent bonder is the XBC300. SUSS has recently achieved some excellent results in the area of thin wafer handling as well.

Tango Systems
Martijn Pierik, of Impress PR, introduced me to the folks at Tango Systems, who were showcasing the company’s flagship PVD system, the Axcela. Ravi Mullapudi, president and CEO, explained how the tool was suited to perform barrier and seed layer processes for TSV, which have been identified as areas still to be addressed from a cost of ownership perspective. He said this dry, vacuum process uses rotating targets in the chamber to perform both steps in one process. The tool can accommodate 150, 200 and 300mm wafers, with quick changover.

Surface Technology Systems
In between catching up on non-industry related news, my good friend Michelle Bourke of STS, clued me in on the companies continued work with improved control of TSV profiles. STS has made lots of progress in maintaining the delicate balance between high etch rates and excellent across-wafer etch depth uniformity. One exciting bit of news she shared with me was the company’s recent R& D success with high speed deep reactive ion etch (DRIE) at 106µm/min. While the process needs to be refined, the point is, they’ve achieved it. So expect to see more on this as the process is tweaked. – F.v.T

IMEC’s Latest Contribution to 3DSiP

Last week, at the Smart Systems Integration conference in Brussels IMEC announced it’s latest 3D SiP technology – the ultra-thin chip package (UTCP). The announcement came while I was at the IMAPS Device Packaging Symposium, which was also being attended by Eric Beyne, scientific director of IMEC’s Advanced Packaging and Interconnect Center, so I asked him for some more details.

Beyne told me the process involves embedding a thinned, 25µm die in polymer film to form a 3D structure. At this stage, Beyne said the Known Good Die (KDG) issue can be addressed, because the chip can be tested through the film. The resulting package is a vehicle for embedding either rigid or flex PCB using standard processes. After embedding, other components, such as a Texas Instrument DSP processor or a wireless sensor can be mounted above and below the embedded chip, leading to high-density 3D integration. If the UTCP is embedded in flexible or even stretchable substrate material, it’s ideal for wearable electronics.

Here comes the really cool part. Beyne explained some of the applications this technology is intended for. One is for measuring brain activity, and interest has been expressed by a hospital that performs epileptic analysis in children. It is less invasive than current methods, which, as Beyne put it, requires the patient to be hooked up with all sorts of wires, and then told to “behave normally.” Kind of hard for a child to do, wouldn’t you think? However, with the UTCP technology, a wireless sensor can be embedded into a stretchable substrate that is part of a hat worn by the child, and transmit signals remotely, so the child can certainly behave normally. Beyne says a similar concept could apply to sleep studies.

Beyne also noted that in the scheme of 3D technologies, these low volume biomedical applications would be difficult to achieve using TSV processes, and is another reason why it makes sense to develop embedded technologies as well. Which is why at IMEC, R&D is largely technology driven. “In the end, we need to have applications to fit the technologies,” noted Beyne. – F.v.T

IMAPS Global Business Council and Device Packaging Symposium in Review

Last week’s event s, held back-to-back at the picturesque Fort McDowell Resort and Casino, Scottsdale, AZ, brought together industry experts, vendors, and academia for a week-long full immersion session in the latest developments of microelectronic device packaging.In addition to the exchange of information and ideas, this remote venue offered attendees and exhibitors a chance to network. Here are a few photos I snapped during some of the social events. Kind of makes you wish you were there, doesn’t it?