ALLVIA – A TSV Success Story

Is ALLVIA ahead of the pack? While the rest of us wonder when through silicon via (TSV) will be ready for market adoption, a small Sunnyvale-based company, ALLVIA, has been chugging right along for the past five years, manufacturing TSVs for a variety of applications like advanced vertical interconnect, silicon interposers for system-in-package, and MEMS sensors. For the past 3 years, they’ve even been generating revenue through prototype services and volume production runs at its fab facility.

Just today, AllVIA announced it has received the third round of funding to allow expansion of the facility and build more capacity. Here. In the US. During a recession. With a technology that’s still, for the most part, trying to break out of the gate. What could be better news than that?

I first met Sergey Savastiouk, CEO of ALLVIA, at IMAPS 2008 and he talked to me about the company’s history. He said he first licensed the technology and developed equipment for TSV processes in 1996, but it drew no interest. So he set about building a foundry to change all that. He even coined the name — through silicon via.

In 2005, ALLVIA began working with customers — MEMS sensors and packaging people — to integrate vias into products and generate missing data. Since then, Savastiouk says the have been working to develop reliability data, costing and manufacturability parameters, which he says are the keys to transport TSVs from niche to volume production.

“As a technology TSVs are going through a similar life cycle as flip chips,” commented Savastiouk. “Flip chips were first developed in the 1960s by IBM. But it took decades to develop the feasibility, reliability, cost effectiveness and manufacturability to get them into volume production. TSV has passed the feasibility phase, but reliability and manufacturability figures, and most importantly, those applications that are willing to pay for the technology, are still being determined.” Savoustiak also said the timeline could be accelerated if a company such as Intel were to lead the charge.

This latest injection of cash – reportedly $5M – brings the company’s investment total to $25M. Looks like ALLVIA is drawing interest now. – F.v.T.

My 3D IC Blog-venture

While most of my blogging will be devoted to talking about what's happening in the world of 3D integration technologies, every once in a while you'll see a post devoted to the blog itself. It's where I explain to visitors, both returning and first-time, what my scope of coverage is, how to submit information for consideration, and tips on how to subscribe. I call it shameless self promotion.

While many of the companies on my radar also have a presence in other market segments, I'll be focusing on their activities as they pertain to 3D IC packaging innovations. So please don't feel slighted if you don't see coverage of a particular press release. It doesn't mean I don't care. I'll do my best to find a connection if there is one. If not, well then, maybe next time. Just keep them coming.

If you're looking for blog coverage serving a broader electronics industry market, check out Gail Writes 4 U. Well-known throughout the electronics industry as editor-in-chief of Advanced Packaging and SMT magazines, Gail Flower has launched her own blog to present coverage in a way that no one else can.

People keep asking how to subscribe to my blog, Françoise in 3D. I've enabled several tools to do this, none of which I'm an expert at explaining how to implement. Mostly I just click on links and follow the instructions. I suggest you try that first. There are two places to do this, at the top of the right hand navigation and after the very last post. There's also an invitation to become a follower. So far I have 3. I'd love for there to be more, so please sign up by clicking the link and following instructions. If all of this baffles you, email me at fvontrapp@gmail and we'll handle it the old-fashioned way. I'll add you to an opt-in subscriber list that will receive email updates once a week. Sound like a plan? -F.v.T

Interview with Steve Lerner: 3D Start-up Alchimer Poised for Success

Talk about good timing. It’s been a whirlwind year of accomplishments for Alchimer, a French semiconductor start-up whose product portfolio is based on nanometric chemical formulations and wet processes for wafer deposition applications. I first got wind of Alchimer’s flagship product, eGViacoat, as a judge for SEMI’s inaugural Best of the West Award program at SEMICON West 2008. Since then, a combination of strategic planning, a one-of-a-kind technology, and loyal investors has Alchimer poised for take-off even in this stalled economy. I caught up with CEO Steve Lerner on Friday, to find out how it all came together.

While eGViacoat is actually the second product in the Alchimer arsenal of three, the strategic decision to target its promotion first was all about timing. Lerner explained that as TSV metallization processes are still being established, the opportunity exists to assume a leadership position where there is no established process.

“This is going to be a hot wave – better than bumping,” says Lerner. “This is an industry-wide wave affecting both front and back-end processes.” He said the company has recipes for via-first, middle, and last processes, as well as TSV for interposers, different substrates and a whole range of dimensions. “We will evolve with the field and provide solutions for everyone; logic, memory, image sensors…” he said.

Alternatively, Lerner explained that eGSeed, the first product developed based on the company’s electrografting (eG) processes, is a dual damascene process that competes with the more complex, established market currently committed to dry PVD and CVD processes. Lerner is confident that Alchimer’s processes can out-perform dry processes at a fraction of the cost, and it’s simply a matter of time before displacing them. Once eGViacoat’s position is secure, Lerner intends to do just that.

The third product (still in beta) is AquiVia, a wet process for isolation, barrier, and seed layer deposition that picks up where Viacoat leaves off. It allows the same tool to be used for insulation, barrier and seed layer deposition, and completely eliminates dry process techniques from TSV metallization resulting in a 70% cost reduction. “It’s all about cost,” says Lerner about TSV adoption. “Quality and design rules are a given, but the overriding driver is cost.” AquaVia is positioned to launch mid-year, and by SEMICON West 2009, all three products will be promoted as a full-line solution.

In addition to the Best of the West Award, eGViacoat has racked up recognition as finalists in both the 2008 Advanced Packaging Awards, and Eurasia IC Industry Awards, and as a top new product for 2008 by Fabtech.

The company announced its first licensing deal with NEXX Systems, provider of electro-deposition systems for TSV applications, for metallization of high-aspect ration TSVs.
Landing its first user licensee , according to Lerner, was the result of meeting with DALSA Semiconductor’s visionary Luc Ouellet. Ouellet analyzed the MEMS manufacturing process and recognized Alchimer’s value proposition as applied to copper TSVs for the company’s low-cost MEMS products. After successful testing, DALSA decided to license the technology.

Lerner scoffs at statements reverberating currently throughout the industry that the front-end is dead and the back-end will follow. He’s been around awhile, and knows that this is all part of the industry lifecycle. Those who make it through will be the ones who are strategically positioned, offer innovative solutions, and are open to collaboration. The semiconductor phoenix will rise again, and Alchimer will assume an active role.

The TGIF 3D Buzz

As my first official week blogging about 3D IC packaging technologies winds down, I'm thinking a Friday wrap-up is in order, and should probably become a regular event. (Being a fly-by-the-seat-of-your-pants kind of person, it's only natural that this blog takes shape as the opportunities present themselves, don't you think?)

Trolling the web for 3D info this morning, I unearthed what I consider to be some noteworthy points of interest. First of all, I found out that NEXX Systems has become a member of SEMATECH's 3D Interconnect Program at the University of Albany's College of Nanoscale Science and Engineering. Specifically, the collaboration will focus on developing high-yield, low-cost copper electroplating processes to enable high-density TSVs. Another thumbs-up for the effectiveness of collaboration.

Next, Ziptronix announced it is developing licensing sGtrategies for it's ZiBond low-temperature covalent bonding and DBI direct bond interconnect technologies across the supply chain, because according to CEO Dan Donabedian, each link in the chain including EDA tool venders, equipment manufacturers, OEMS, IDMS, chip manufacturers and foundries, stand to gain something from these processes. Look for an in-depth interview on these developments next week.

Two additions to the event calendar include MEPTEC's Semiconductor Packaging Symposium, which, among other things, touches on latest developments in 3D technologies that have made it to full production: PoP stacks, and TSV for CMOS image sensors; and EMC3D Consortium's Asia Tour, which will focus on latest advancements in 3D integration using TSV technology from trends and roadmaps, to performance requirements, cost-effective applications and more.

And finally, while she says it's not "new" news, Gretchen Patti, of Tezzaron Semiconductors, passed along an interesting paper she penned that's worthy of attention as it touches on an advantage of 3D ICs that I had yet to see listed among the usual laundry list of benefits. Evidently, by nature they offer security benefits in two ways. Due to the layered manufacturing processes, their circuitry is virtually impossibly to decipher during manufacture, and fully assembled 3D ICs defeat reverse engineering. For the full story, download 3D-ICs and Integrated Circuit Security. - F.v.T

3D technology research gets another shot in the arm

It looks like it's 3D to the rescue again. I love it. Yesterday, a collaboration was announced by Semiconductor Research Corp. and Georgia Tech that involves the creation of the Interconnect Packaging Center (IPC). The center will be located at Georgia Tech in the Marcus Nanotechnology Building, and will involve the combined efforts of programs at Georgia Tech, Harvard, The University of Texas at Austin, Iowa State University and Singapore's Nanyang Technological University (NTU).

The goal is to develop interconnects that have improved communication between different chips via packaging while achieving an overall reduced chip footprint. And joy of joys, half of the research will focus on new 3D technologies.

This is the second 3D-focused, industry-academia project operating out of Georgia Tech. The 3D All Silicon System Module (3DASSM) Consortium, set to launch early this year, is a combined effort of Georgia Tech’s Microelectronics Packaging Research Center (PRC), the Fraunhofer IZM, KAIST, and (to date) 14 participating companies. Unlike the new IPC, the focus of this work is on packaging, not 3D ICs, and involves work with silicon interposers, wafer-level packaging, and thin-film embedded components to ultimately integrate the IC, package and board seamlessly.

So while not directly related to the collaboration with SRC and Georgia Tech, it certainly poses some interesting synergies. Rao Tummala must be dancing in the streets.

SEMIspice: Five reasons to exhibit during a recession

Be sure to check out SEMIspice: Five Reasons to Exhibit During A Recession. Tom really hits the nail on the head. There's never a more important time to maintain a vital presence in the industry than during a financial crisis. There are certainly other places to tighten the belt than your marketing budget.

Oerlikon streamlines for 3D and solar

Oerlikon’s double-barrel news about the sale of its Oerlikon Esec business unit to BESI, and expected management buyout of its etch unit brings to fruition strategic plans I got wind of in October at SEMICON Europa. At that time, Sven Jarby, who heads up marketing and communications for Oerlikon Balzer’s Coating, alluded to the company’s strategic plans to focus on applications that appeal to its core competencies; thin film and coating for TSV processes and solar panels.

By divesting itself of its only traditional back-end semiconductor unit, the wire and die bonder business, Dr. Uwe Krüger, CEO of the Oerlikon Group, says “Oerlikon has significantly reduced its exposure to the cyclical semiconductor market.” It becomes more apparent as companies align themselves vertically that knowing what your company’s core competencies are and focusing on those is a good way to carve a niche in the future of the industry.

The other ponderable question is what BESI will do with Oerlikon Esec’s die bonder division. The organization already holds a strong market position in the die bonder arena with Datacon. According to a press release from BESI, the Esec brand name will be retained, and plans are underway to leverage synergies between the two companies. I'll be curious to find out what becomes of the Oerlikon Esec/Muehlbauer alliance that was announced in November, which was intended to provide turnkey solutions for the smart card module industry. It’s no secret that Datacon is firmly established in RFID technologies. Will this make for strange bedfellows or will it be a merging of the minds? I’ll be keeping my eye on this one.