NEXX Systems: Going Strong in Tough Times

View slide show of my visit to NEXX

It’s easy to see why NEXX is experiencing growth. It’s all about attitude, and the enthusiasm among NEXX’s team is contagious. I spent yesterday afternoon (Thursday, March 5) visiting the company’s new headquarters in Billerica, MA, meeting with the executive team, and touring the manufacturing facility. The team had lots of exciting news to share, and brought me up to speed on the technology, tools, and what CEO and president Tom Walsh called their “roadmap alignment” for the Stratus line of plating tools.

Strategic Collaborations
NEXX has always seen the benefits of collaboration. For smaller companies in a big pond, it helps to level the playing field and leverage know-how. Senior project manager, Mark Welsh, talked to me about current collaborations with SEMATECH’s 3D Interconnect program and IMEC's Industrial Affiliation Program (IIAP) on 3D integration. Welsh explained that unlike equipment/supplier programs, which focus on educating IDMs and OSATS on new processes, these joint development programs (JDPs) allow affiliates to learn what the end user’s future requirements will be, and work toward that goal. “The IMECs or SEMATECHs are driving the design of the process flow,” he explained.

In the case of SEMATECH’s program, NEXX will collaborate on developing innovative electrodeposition technology for high-yield, low-cost copper electroplating to enable high-density 3D through-silicon-vias (TSVs). Research with IMEC will focus on joint R&D for TSV metallization and micro-bumping. Both efforts involve the Stratus line.

And there’s more. The team was fairly bursting with news of the latest collaboration that will be announced during IMAPS Device Packaging Symposium this week. All they could tell me at that time was that it involves a major IDM and will really launch the company into the limelight. Trust me, as soon as I know, you’ll know.

Technology Progress
Although not the only technology story to tell, TSVs process developments are at the top of NEXX’s list. Arthur Keigler, V.P. of technology talked to me about the “second phase” of work the company has been doing with the Stratus line to lower the cost-of-ownership. “We’re working on a new module technology that will reduce chemistry consumption for the process,” he said.

Also in testing phases is a process for pre-treatment of wafers prior to filling them for better control of surface chemistry in the vias. The structure of the Stratus Line, which is based on a vertical orientation of the wafer and is modular, is ideally suited to this process because it allows for what Walsh calls a “multiple sequencing capability.” Additionally, with the wafer in a vertical orientation, bubbles are less likely to get trapped in the vias, reducing the possibility of voiding.

The process flow goes like this: The first set of cells perform the conformal plating process for uniform coverage of even hig-aspect ratio vias. In the second cell set, vias are super-filled most of the way, and then the process slows to minimize a possible “mound” effect.

Walsh explained that in the traditional “fountain cell” system, in which cells are horizontal, the process would call for additional cells to be added to the system, changing the footprint of the tool. Alternatively, this multistep solution for TSVs allows for the most wafer-outs in a small footprint. In terms of productivity, this vertical mode is it.

Recent work with Alchimer, whose process and chemistries NEXX has licensed, is focused on copper barrier-on-plate using a wet process. The application that will benefit most from this work is high-aspect ratio vias. Other applications served by NEXX tools and processes include lead-free, UBM for copper pillar bumping, and micro-bumping. In fact, the work with the IDM-who-must-not-be-named will focus on micro-bumping processes.

Roadmap of Alignment
Walsh told me that last year’s focus was on the Stratus. The “Roadmap of Alignment” has included formalizing engineering methodologies to make the Stratus the production-worthy tool-of-choice. They’ve also formalized processes for in-house testing, and have aligned with the needs of suppliers to develop throughput and speed enhancements.;

While much of my visit focused on developments with the Stratus tool, NEXX’s PVD tool family deserves some ink. Although a mature product, there is a subtle roadmap in place for them. The Apollo, lunched last year at SEMICON West, features better particle control, etch uniformity and thin wafer handling. Target applications here include handling wafers as thin as 100µm for applications such as Backside Metal (BSM). Additional handling applications include non-silicon and highly bowed substrates for build-up and eWLB processes.

Business model for success
At the end of the day, success is all about serving the customer. In the 3D space, customers are putting their investments into the development side. “We’re working with them,” says Walsh.“Their motivation is where we want to be.” It’s important, he said, to keep up the enthusiasm.

Part of NEXX’s model, he says, is to support the customers locally. For example, for one major Taiwanese OSAT-who-must-not-be-named, NEXX has a local group, including an applications engineer and a process engineer, in place to provide service and support.

During these times, it’s especially important to provide great service to customers and build relationships,” says Walsh. “Our success model is based on delivering solutions through product, services and support.” The model must be working, because business is hopping at NEXX Systems. – F.v.T

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Happy Birthday, IMEC!

I finally realized why I find the semiconductor industry so compelling, and why the people are so great to work with. It’s because it’s made up of people who like to fix things and find solutions. This came to me while I was reading this morning’s email, which included an announcement of IMEC’s 25 Anniversary Celebration, which takes place as part of this year’s IMEC Technology Forum (ITF2009) from June 2-4, 2009. The announcement talked about how consumers rarely think about what goes into creating the devices that they have come to rely on to conduct their lives. “Executives managing the world’s leading high-tech companies are constantly monitoring problems and trends and thinking of solutions for each one. After all, engineers and scientists are fix-it people.” This is not an industry of complainers. This is an industry of pro-active trend-setters.

Therefore, it makes perfect sense that rather than reflecting on the past 25 years, the ITF will celebrate IMECs 25th anniversary by highlighting the theme of science and technology innovation for the next 25 years. The program will feature experts from IMEC and within the industry who will discuss their vision and startegies on both scaling and non-scaling activities, changes in business approach, and collaboration opportunities with R&D centers.

In addition to presentations, highlights of the 3-day event include a reception at IMEC’s state-of-the-art campus, two panel discussions about advancements in the biomedical and photovoltaic domains, a walking dinner followed by a contemporary classical recital of Wim Mertens, and wrapping up with talks from IMEC’s experts covering “The 10 nanometer device”, “Heterogeneous integration”, “Semiconductor technology for the next generation and conversion of renewable energy”, “Wireless and optical communication” and “Human++: merging biology and electronics for a better life.”

This sounds like the perfect way to celebrate such an important milestone. Let me be among one of the first to congratulate the people at IMEC on what they have achieved, and wish them 25 more innovative years. We all stand to benefit from what they do. – F.v.T.

The Other 3Ds: Occam Process

The brainchild of Joe Fjeldstad, Verdant Electronics, Occam Process got a lot of ink in the press when it was first introduced in 2007. I should know. I recruited several articles from Fjelstad myself for publication in Advanced Packaging Magazine. During an advisory board luncheon at SEMICON West, Fjelstad sidelined me to tell me about the 3D assembly process, which involves a reverse-order interconnect process implemented using existing materials and equipment, resulting a solder-free assembly that is said to achieve such high reliability that Fjelstad jokes about it passing a “throw test” rather than a “drop test.”

Since the initial media frenzy that occurred as all the electronics assembly and packaging publications scrambled to be the “first” or the most “in depth” or even the “most controversial” sources of coverage, Occam has faded from the press limelight. However lack of coverage doesn’t necessarily mean lack of progress, and recent correspondence I received from Harvey Miller, of IEEE, brought Occam duly back on my 3D radar. He shared an article he wrote for PCBOO7, which thoroughly explains what Occam is and what it isn’t, and why Miller endorses Occam as having “the potential to transform electronic manufacturing and restore the competitive position of U.S. and North America as creators of real value.”

I caught up with Fjelstad yesterday. He told me that concepts are beginning to evolve, and pointed out several particularly active areas of interest. “Nacent projects are underway with the Navy,” he said. “They are beginning to develop their own assembly processes based on Occam.” The second area of “burgeoning interest” is in LED lighting. Lead-free materials are an issue with lighting assemblies, because the temperatures are too high, so solder assemblies are running into problems. The solder-free aspect of the Occam prcess makes it a perfect technology for lighting. Interest is also heating up in the automotive industry.

In semiconductor packaging, the Occam Process allows for an innovative 3D stacked package configuration Fjelstad refers to as package-under-package (PuP). “There is possibility to take existing packages and affix one beneath the other creating a PuP and presenting them for assembly using standard SMT processing.” He explained. The module examples shown here include ability to provide metal jackets for shielding and thermal relief.

If the amount of interest can be measured in requests for presentations and keynote addresses, then things are looking good for the future of Occam. ”I gave a presentation yesterday to a room full of top-level technologists from top-tier companies and got a good deal of head nodding during my talk,” noted Fjelstad. “It has wings of its own.” Here’s to a successful flight. – F.v.T.

3D EDA Tools – Coming out of the Woodwork

That didn’t take long. A post about one EDA tool introduction inspired a comment about a 3D layout editor that’s been on the market for 2 years. A mention of said comment in Tuesday’s email update and an email to the individual who posted the comment brought immediate response. This is the beauty of blogging; it results in an almost instantaneous sharing of information and inspires collaboration.

According to Mark Mangum, sales manager for EDA tools and chip design tools at Micro Magic, Inc, the company’s layout editor, MAX 3D, handles the physical design of the chip, and is particularly suited to TSV design. He explained that its ability to manage separate wafer levels with individual tech files is more effective than relying on a "super tech file" to handle the whole design. With this approach, each wafer level maintains its own tech file throughout the design process.There is an additional tech file for the interconnect. In addition, the tool’s speed and capacity is ideal for handling the size and complexity of TSV designs. A slower editor tends to decrease performance drastically.

Three important elements of good EDA tools are programmability, customizability, and compatibility with other tools in the toolbox. Mangum assured me that MAX 3D was developed with these considerations in mind. “Integration is a key selling point for our customers, so we've made an effort to make our tools work with others.” he said, adding that the tool was developed for “open architecture”, with ASCII data files and open source scripting language. OpenAccess support was added for design data files due to customer demand, and is continually updated. To handle Pcell design data, a Pcell interpreter from IPL was added to allows users to read their Pcell data. "MAX-3D has real time design rule checking (DRC), but because many customers use Mentor Calibre for signoff DRC, a direct interface to Calibre was added. We also support industry standard file formats such as GDSII, LEF, DEF, etc. so MAX-3D users won't have to worry about "vendor lock-in" of file formats - for design data, cells, or generators,” he said.

Mangum told me MAX-3D is being used by several universities, including MIT, Lincoln, Cornell, North Carolina State, Penn State. Six companies have also incorporated it into their processes, mainly for developing test chips.

Are there other 3D tools in the works at Micro Magic? Mangum says yes, but is hush-hush about it. "We are working on some packaging-related development with a customer, but no word on when we'll be discussing it," he said. Simulation and verification are big blind spots in the industry right now, he added, but rumor has it, Mentor has something in the works on this.

I know one of Micro Magic’s customers is happy with the performance of the company's tools. An unsolicited endorsement appeared in my inbox shortly after I mentioned the product in my email. Gretchen Patti, technical communications specialist for Tezzaron Semiconductor, stated simply, yet enthusiastically. “About Micro Magic: Their tools are real! We use them.” That’s pretty much all I needed to know. – F.v.T.

The Skinny on 1st Lighten the Load Inc.

First of all – I LOVE the name of this company. For that reason alone, I was intrigued enough to find out more about it, and where it fits in the 3D space. Remember, 3D integration is not only about stacking chips and devices vertically to fit more functionality into less space, it’s about utilizing what ever space is available in the z-direction – which can mean embedding passives and actives into substrate materials, or using conductive inks to get the most out of device real estate. In the case of 1st Lighten the Load, we’re talking about a disruptive technology using printed electronics fabrication to reportedly eliminate the need for 95% of passive components. With this fabrication technology, passive components no longer have a structure of their own, but rather are integrated into an electronics assembly ¼ the thickness of a PCB.

Dave Kelly, CTO of 1st Lighten the Load, Inc. responded to my query for more information on his company’s technology with the following main points:

Passive parts are now printed ink, eliminating their body and allowing them to be incorporated into lower assembly layers.

The metal traces are metal not conductive ink, with low resistance and as thin as 1 nanometer.

Vias are printed and can be placed without restriction in lower layers.

The assembly uses a solid core to control thermal expansion eliminating mechanical stress on integrated circuit die and spreading heat.

The chips can use flip chip or other bonding attachment method to the assembly.

The number of layers of stacked chips and layers is unlimited.

The metalization can be fabricated with traces much less than 25µm wide and 25µm spaces.

Although originally designed to manufacture ultra-high density capacitors, the first two markets being targeted for this technology are the capacitor industry and high-volume electonics fabrication. Ultra-high density capacitors will follow, with the automotive industry slated next, and ultimately universal personal electronic devices (UPED). A detailed paper about 1st Lighten the Load's technology, licensing opportunities and future plans is available.

Licenses for the technology are now available, and Kelly reported that discussions are in the works with several companies and investors to set up a pilot manufacturing line. I’ll be sure to follow this one as it grows. F.v.T.

Weekend 3D Buzz

I know - I KNOW! I missed my first Friday, and I felt just terrible about it. But hey, I have a valid excuse — several, in fact. I finally sold my house after 11 months on the market (29 showings in January alone, and 9 in February - do the math). So I took some time to get organized for the move, which will happen in about 6 weeks.

In addition, I started to work on the next phase of my 3D plan, of which this blog is merely one dimension. That's all I can say for now, but I'm hoping to have an unveiling of sorts just befor the Device Packaging Symposium in Scottsdale - which is only 2 weeks away. (I'd better get cracking!).

So if things appear to slow down for a few weeks, please stay tuned. A lot is going on behind the scenes - and this is just the quiet before the storm. In the mean time, keep the 3D news coming this way! I'll do my best to keep up.

Bluebird: A project in 3D Equipment Development

I consider myself to be fairly savvy when it comes to knowing who the players are in 3D IC technology research, so when I first saw the news article in EDN reporting that TNO, an Eindhoven-based scientific research company, had approached BESI/Datacon to develop a high-end pick-and place tool for die-to-wafer (D2W) stacking, I felt a bit chagrined; I had never heard of TNO. So I set out to find out as much as I could. It occurred to me that maybe there were others like me out there who had been in the dark.

Bluebird Basics
It turns out that TNO has a fairly broad reach in scientific research, with one arm extending into the development of high-end equipment for specific markets. One of the projects falling under this division is the Bluebird Project, led by R.M.W. (Roger) Gortzen. Its aim is to develop integrated equipment for the purpose of manufacturing 3D IC devices cost effectively and at high volume.

According to the website page about the program, this equipment is intended for 3D stacking using TSVs, rather than wire bonding, as the method of interconnect. Gortzen talks about an integrated system with processed wafers prior to via construction as input, and outputs stacked die. Steps to be eliminated include optical inspection, wafer feeders, transportation between separate machines, and some materials. The long-term goal of this project (target completion 2016) is to achieve stacked-die 300 mm wafers at $100/wafer.

To this end, Gortzen has worked with IMEC to identify the current bottlenecks in the process. The first phase will focus on standardization for the project, thin wafer and die handling, pick and place for die-to-wafer (D2W), bonding, and particle inspection.

Enter BESI/Datacon
Gortzen has clearly been listening to other players in the industry. Citing presentations given at IMAPS 2008, SEMICON West, and by members of EMC3D, here’s what he heard; there isn’t a tool on the market that is appropriate to stack 3D packages. He proposes that a new platform design with more placement-per-second and higher-accuracy aligment at low cost is required. This brings us to the recent news about the collaboration with BESI/Datacon.

Datacon brings experience in advanced D2W technologies, as they have been collaborating on these processes for quite some time with EV Group. That work resulted in a toolset consisting of high-volume flip chip bonding equipment for a pre-bond process, at which point fully assembled wafers were transferred to a die-to-wafer bonder for permanent bond.

Hannes Kostner, of BESI, was happy to answer some questions regarding BESI/Datacon’s involvement in Bluebird. “The project between BESI/Datacon and TNO is one part of Bluebird,” he explained.”This subproject is called BlueHawk and the target is to develop a high accuracy flip chip bonder with a placement accuracy of the already mentioned 2.5µm at 3sigma.”

I asked why a project targeting TSV stacking would be based on a flip chip platform. He explained that Datacon’s 8800 FC Quantum is a perfect platform to start a high accuracy development because it already achieves a performance mix of throughput and accuracy in the order of 10µm at 3sigma at approx. 8000 uph. Additionally, he said it’s not to a drawback to start from a flip-chip only machine, because it’s really just a question of presenting dies on the dicing tape for D2W production. “A flip chip machine is potentially faster since the handling of dies is split into two parallel processes; ejection and flipping and measurement and placement,” he said. With this process, Kostner said the TSVs are formed before die placement so the diebonder can handle the current TSV approach.

A prototype of the TNO/BESI/Datacon tool is scheduled for introduction by the end of this year, with commercial launch sometime in 2010. The companies say they are confident that this tool will be the production tool of the future for D2W processes in the emerging market of 3D stacking.

So there you have it. Now you know what I know. And now that the Bluebird project is on my radar, I’ll be sure to stay on top of it.–F.v.T.