TSVs: just the tip of the 3D ICeberg

At ECTC last week, I counted at least 21 presentations dedicated to TSVs alone, and 13 dedicated to other processes for 3D IC integration. The sheer volume and depth of research required around bringing these technologies to market is sometimes lost on those of us who sit outside the circle of academia and research, and only hear about those that make it to marketability. And although TSVs have become the poster child for 3D IC integration, sometimes we forget that there are other steps of equal importance to achieving these 3D stacks; namely backgrinding, thinning and dicing; temporary bonding and debonding for both wafer-to-wafer (W2W) chip-to-wafer processes (C2W); and chip stacking.

According to IMEC’s Eric Beyne, while many companies are involved in developing materials and equipment for TSV processes (etch, seed layer, fill, etc.) there are only 2 equipment manufacturers (EV Group and SUSS MicroTec) that offer tools for temporary bonding and debonding processes, and only a few materials companies (Brewer Science, 3M, and Dupont) developing temporary bonding materials. Beyne described one temporary bonding material that when heated, allows the device wafer to slide apart from the carrier wafer; and another that vaporizes the material holding them together. Unfortunately, both of these materials involves high temperatures, which, when used in sequential processes to achieve multiple chip stacks, can stress the ultrathin device wafers. Therefore, IMEC is working on a parallel process to overcome address this. One approach is to stack the chips using a sort of stencil to maintain alignment, and then perform the bond step all at once.

Chip stacking is another step still requiring some solutions in C2W processes, where the perfect combination of speed and accuracy is yet to be achieved. S.E.T has developed a high-precision, flexible die bonder that reportedly achieves a throughput of 150pph, earning the company installs at IMEC, SEMATECH and CEA-Leti; but according to Mike Thompson, CTO of Replisaurus, S.E.T’s parent company, that number needs another zero (1500) to make it volume-production-capable. Solving this alignment plus throughput conundrum is the focus of TNO’s Bluebird project with Datacon. As part of the EMC3D consortium, EV Group is also working with Datacon to solve the C2W stacking issue.

What’s not being revealed is likely to be more important than what is being revealed. As was pointed out to me on more than one occasion last week, companies aren’t likely to talk about what they’re working on until it’s a done deal. And they never talk about what they’ve tried that has failed, which could ultimately be as useful for competitors to know about as the successes are. In any case, it appears that there’s still work to do before all the stars align. – F.v.T.

Following the 3D innovation path to profitability

In last week’s email update, I talked about the pendulum starting to swing back the other way, albeit ever so slightly. It’s little things, such as SEMI’s book-to-bill rising from a frightening .48 to a less ominous .61; to bigger things, like TSMC announcing they will invest in R&D despite a hiring freeze in other sectors. As part of it's roadmap to innovate its way out of the slump, the company claims it will have its 300mm fab ready to manufacture TSVs by June. This is exciting news for equipment and material suppliers who have committed to investing in TSV processes.

Whether or not you're a proponent of TSV, it’s clear that companies who are investing in those technologies are faring better these than those who are hacking away at the bottom line to weather the storm. It seems to be working for SUSS MicroTec and EV Group, who have both invested in developing tool sets for wafer bonding, lithography, and mask aligning for the 3D IC integration market. Last week, SUSS announced an order from Nemotek Technologie for multiple lithography systems to be used for manufacturing the company’s CMOS images sensors (CIS). As CIS was the first application to adopt TSV processes in volume production, this win helps establish SUSS as an equipment provider for CIS.

On the heels of that news, came EV Group’s announcement that they will increase production capacity due to “strong order intake” driven by R&D investment in the 3D IC and nanoimprint lithography markets. EV Group strategically established itself in academia, shrewdly anticipating that while capex spending would fall off in the public sector, universities and research institutes would be investing in 3D IC integration to be ready for the rebound.

In his recent SemiSpice blog post, Tom Morrow recounts the different approaches taken by both Kelloggs and Post to survive the Great Depression. Reading it, I thought of Lam Research and Applied Materials (AMAT), equipment vendors who both offer etch tools for 3D IC applications. See if you can guess who is the Post and who is Kelloggs in this scenario. In December 2008, AMAT made headlines with its launch of the Silvia etch tool, then joining EMC^3D and most recently entering into a joint development agreement with Disco to develop wafer thinning processes for TSVs. The only news I’ve seen about Lam in the same time frame is a layoff of 600 employees in November, and another 375 in March. Both layoffs were part of a plan to reduce Lam’s cost structure. In December, Applied announced a cash dividend, while in April, Lam announced a quarterly loss.

While cost cutting may help the bottom line in the short term, it’s my experience that in the long run, innovation and investment goes a lot further to improve a company’s image and ultimately its bottom line, not to mention establish company moral and loyalty. Kudos to the companies and organizations that choose not only to invest and innovate, but also publicize accomplishments. It gives us all something to strive for. -- F.v.T.

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Notes from the Exhibition Hall

I have to admit that this year at IMAPS Device Packaging Conference, I spent more time attending technical sessions and less time with the exhibitors than I usually do at an industry event. However, I did manage to check in with a few of them to see what their latest contributions are to the 3D IC and 3D Packaging realm.

Palomar Technologies
I wasn’t surprised to run into Bradley Benton at the Palomar booth – I pretty much expect to see him at these events. In fact, he gave me my first comprehensive lesson in the history of wire bond technologies. I was, however, surprised to learn that the company, which is firmly established in the wire bond business, is venturing into the TSV space with its 6500 Eutectic Die Attach System. Benton says the tool is designed to perform die to wafer processes, and achieves 1.5 µm placement accuracies.

“We recognize that TSV is coming,” he noted. “We have some TSV capabilities now. We’re looking into ways of enhancing that.” Benton says his interest in 3D packaging is why he got into this business 26 years ago. “I always assumed microelectronics would build up and not out.” He said. “What’s new is that we’re finally going at it and doing it with silicon.

SUSS MicroTec
I caught up with Kathy Cook of SUSS MicroTec at the tail end of the poster sessions on Thursday, where she was presenting a poster based on Margarete Zoberbier’s recent presentation at SEMICON Korea about some of SUSS’ equipment technologies for TSVs. Cook explained that polymers adhesives may be necessary for permanent bonding when copper alone isn’t enough to hold the wafers together. The take-away message was the company’s achievement of submicron post bond alignment accuracy (.35µm) for permanent bonding and several other new capabilities involving SUSS’s latest 300mm tools – ACS300 Gen 2 Coater and the MA300 mask aligner. The 300mm permanent bonder is the XBC300. SUSS has recently achieved some excellent results in the area of thin wafer handling as well.

Tango Systems
Martijn Pierik, of Impress PR, introduced me to the folks at Tango Systems, who were showcasing the company’s flagship PVD system, the Axcela. Ravi Mullapudi, president and CEO, explained how the tool was suited to perform barrier and seed layer processes for TSV, which have been identified as areas still to be addressed from a cost of ownership perspective. He said this dry, vacuum process uses rotating targets in the chamber to perform both steps in one process. The tool can accommodate 150, 200 and 300mm wafers, with quick changover.

Surface Technology Systems
In between catching up on non-industry related news, my good friend Michelle Bourke of STS, clued me in on the companies continued work with improved control of TSV profiles. STS has made lots of progress in maintaining the delicate balance between high etch rates and excellent across-wafer etch depth uniformity. One exciting bit of news she shared with me was the company’s recent R& D success with high speed deep reactive ion etch (DRIE) at 106µm/min. While the process needs to be refined, the point is, they’ve achieved it. So expect to see more on this as the process is tweaked. – F.v.T

NEXX Systems: Going Strong in Tough Times

View slide show of my visit to NEXX

It’s easy to see why NEXX is experiencing growth. It’s all about attitude, and the enthusiasm among NEXX’s team is contagious. I spent yesterday afternoon (Thursday, March 5) visiting the company’s new headquarters in Billerica, MA, meeting with the executive team, and touring the manufacturing facility. The team had lots of exciting news to share, and brought me up to speed on the technology, tools, and what CEO and president Tom Walsh called their “roadmap alignment” for the Stratus line of plating tools.

Strategic Collaborations
NEXX has always seen the benefits of collaboration. For smaller companies in a big pond, it helps to level the playing field and leverage know-how. Senior project manager, Mark Welsh, talked to me about current collaborations with SEMATECH’s 3D Interconnect program and IMEC's Industrial Affiliation Program (IIAP) on 3D integration. Welsh explained that unlike equipment/supplier programs, which focus on educating IDMs and OSATS on new processes, these joint development programs (JDPs) allow affiliates to learn what the end user’s future requirements will be, and work toward that goal. “The IMECs or SEMATECHs are driving the design of the process flow,” he explained.

In the case of SEMATECH’s program, NEXX will collaborate on developing innovative electrodeposition technology for high-yield, low-cost copper electroplating to enable high-density 3D through-silicon-vias (TSVs). Research with IMEC will focus on joint R&D for TSV metallization and micro-bumping. Both efforts involve the Stratus line.

And there’s more. The team was fairly bursting with news of the latest collaboration that will be announced during IMAPS Device Packaging Symposium this week. All they could tell me at that time was that it involves a major IDM and will really launch the company into the limelight. Trust me, as soon as I know, you’ll know.

Technology Progress
Although not the only technology story to tell, TSVs process developments are at the top of NEXX’s list. Arthur Keigler, V.P. of technology talked to me about the “second phase” of work the company has been doing with the Stratus line to lower the cost-of-ownership. “We’re working on a new module technology that will reduce chemistry consumption for the process,” he said.

Also in testing phases is a process for pre-treatment of wafers prior to filling them for better control of surface chemistry in the vias. The structure of the Stratus Line, which is based on a vertical orientation of the wafer and is modular, is ideally suited to this process because it allows for what Walsh calls a “multiple sequencing capability.” Additionally, with the wafer in a vertical orientation, bubbles are less likely to get trapped in the vias, reducing the possibility of voiding.

The process flow goes like this: The first set of cells perform the conformal plating process for uniform coverage of even hig-aspect ratio vias. In the second cell set, vias are super-filled most of the way, and then the process slows to minimize a possible “mound” effect.

Walsh explained that in the traditional “fountain cell” system, in which cells are horizontal, the process would call for additional cells to be added to the system, changing the footprint of the tool. Alternatively, this multistep solution for TSVs allows for the most wafer-outs in a small footprint. In terms of productivity, this vertical mode is it.

Recent work with Alchimer, whose process and chemistries NEXX has licensed, is focused on copper barrier-on-plate using a wet process. The application that will benefit most from this work is high-aspect ratio vias. Other applications served by NEXX tools and processes include lead-free, UBM for copper pillar bumping, and micro-bumping. In fact, the work with the IDM-who-must-not-be-named will focus on micro-bumping processes.

Roadmap of Alignment
Walsh told me that last year’s focus was on the Stratus. The “Roadmap of Alignment” has included formalizing engineering methodologies to make the Stratus the production-worthy tool-of-choice. They’ve also formalized processes for in-house testing, and have aligned with the needs of suppliers to develop throughput and speed enhancements.;

While much of my visit focused on developments with the Stratus tool, NEXX’s PVD tool family deserves some ink. Although a mature product, there is a subtle roadmap in place for them. The Apollo, lunched last year at SEMICON West, features better particle control, etch uniformity and thin wafer handling. Target applications here include handling wafers as thin as 100µm for applications such as Backside Metal (BSM). Additional handling applications include non-silicon and highly bowed substrates for build-up and eWLB processes.

Business model for success
At the end of the day, success is all about serving the customer. In the 3D space, customers are putting their investments into the development side. “We’re working with them,” says Walsh.“Their motivation is where we want to be.” It’s important, he said, to keep up the enthusiasm.

Part of NEXX’s model, he says, is to support the customers locally. For example, for one major Taiwanese OSAT-who-must-not-be-named, NEXX has a local group, including an applications engineer and a process engineer, in place to provide service and support.

During these times, it’s especially important to provide great service to customers and build relationships,” says Walsh. “Our success model is based on delivering solutions through product, services and support.” The model must be working, because business is hopping at NEXX Systems. – F.v.T

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GBC 2009 - A 3D Packaging Junkie’s Dream

When I opened Lee Smith’s email yesterday to find the updated agenda for Spring 2009 IMAPS Global Business Council, I thought maybe I’d died and gone to 3D heaven. Called “Supply Chain Development for 3D Packaging”, the agenda for this one-day event preceding the Device Packaging Symposium is jam-packed with keynote-level speakers whose presentations span the 3D spectrum, giving air time to much more than the latest in TSV, although it certainly gets its due. Committee co-chairs, Lee Smith, VP of business development at Amkor, and Jie Xue, Ph.D. director of technology and quality at Cisco Systems, Inc. have done such a stellar job of putting together a content-rich program that I predict standing-room-only.

"I am very pleased with the overwhelming support we received from industry experts to speak at this event,” says Smith. “I've been involved with 3D packaging from folded flex assemblies to TSV interconnects over the past 28 years and believe this conference is a must-attend for anyone who is looking to develop, use or supply 3D IC, TSV or 3D packaging technologies.” He added that the GBC forum’s high level of speakers and attendees fosters open communication and is unique because rather than discussing technologies or products, the focus is placed on the business and logistics issues associated with developing a capable supply chain, which is critical to both users and suppliers.

This year Jan Vardaman, president, TechSearch International sets the tone with her keynote, “Market Demand, Applications, and Requirements for 3D Packaging and 3D ICs”. The morning session focuses on supply chain collaboration from R&D to commercialization of 3D ICs with TSVs beginning with "The Role of Consortia", featuring presentations by Rosalia Beica of EMC3D, and Eric Beyne of IMEC. Next, executives from several IC suppliers offer their perspectives. Among them, Bob Patti, of Tezzaron offers insight as an early supplier of 3D IC products, talking about obstacles his company faced due to lack of supply chain infrastructure.

During lunch, Bill McLean of IC Insights will offer a keynote on an upbeat topic, “Poised for Quick Rebound”. Hopefully this will help boost attendee optimism about the economic climate, or at least get us through desert without causing a room full of indigestion.

The afternoon is divided into two sessions, “3D Packaging, TSV, Roadmap, and Supply Chain/Technology Development” and “Multi-sources of Supply and Lessons Learned from 3D Packaging-based Products”. Here’s where other 3D flavors share the spotlight with TSV. Bill Bottoms of Nanonexus will talk about system-in-package (SiP) integration for 3D, Bob Lanzone of Amkor will unveil the company’s next-generation package-on-package (PoP) built on its proprietary through mold via (TMV) technology platform, and Marc Robinson, CTO of Vertical Circuits, will no doubt at least touch on the company’s jetted silver-filled polymer interconnect technology for chip stacking in his presentation, “Rolling Out a New Packaging Technology; Maximizing Supply Chain Opportunities.”

For maximum value, Smith recommends that technologists and business leaders consider coordinating their companies participation in the GBC and the two and a half days of strong 3D technical papers and exhibits that follow at the IMAPS Device Packaging Conference. “Within Amkor, we see the GBC and DPC as our top conference for 2009 participation; due to the quality of the topics, speakers, attendees," he says. "and of course our Arizona weather in March is a huge draw."

Let’s see, all the 3D I could possibly want to know about; a 3-day exchange of ice and snow for warm sunshine… I’ve heard enough. Come March 8-11, you know where to find me and my laptop. Hope to see you all there. – F.v.T

ALLVIA – A TSV Success Story

Is ALLVIA ahead of the pack? While the rest of us wonder when through silicon via (TSV) will be ready for market adoption, a small Sunnyvale-based company, ALLVIA, has been chugging right along for the past five years, manufacturing TSVs for a variety of applications like advanced vertical interconnect, silicon interposers for system-in-package, and MEMS sensors. For the past 3 years, they’ve even been generating revenue through prototype services and volume production runs at its fab facility.

Just today, AllVIA announced it has received the third round of funding to allow expansion of the facility and build more capacity. Here. In the US. During a recession. With a technology that’s still, for the most part, trying to break out of the gate. What could be better news than that?

I first met Sergey Savastiouk, CEO of ALLVIA, at IMAPS 2008 and he talked to me about the company’s history. He said he first licensed the technology and developed equipment for TSV processes in 1996, but it drew no interest. So he set about building a foundry to change all that. He even coined the name — through silicon via.

In 2005, ALLVIA began working with customers — MEMS sensors and packaging people — to integrate vias into products and generate missing data. Since then, Savastiouk says the have been working to develop reliability data, costing and manufacturability parameters, which he says are the keys to transport TSVs from niche to volume production.

“As a technology TSVs are going through a similar life cycle as flip chips,” commented Savastiouk. “Flip chips were first developed in the 1960s by IBM. But it took decades to develop the feasibility, reliability, cost effectiveness and manufacturability to get them into volume production. TSV has passed the feasibility phase, but reliability and manufacturability figures, and most importantly, those applications that are willing to pay for the technology, are still being determined.” Savoustiak also said the timeline could be accelerated if a company such as Intel were to lead the charge.

This latest injection of cash – reportedly $5M – brings the company’s investment total to $25M. Looks like ALLVIA is drawing interest now. – F.v.T.

Interview with Steve Lerner: 3D Start-up Alchimer Poised for Success

Talk about good timing. It’s been a whirlwind year of accomplishments for Alchimer, a French semiconductor start-up whose product portfolio is based on nanometric chemical formulations and wet processes for wafer deposition applications. I first got wind of Alchimer’s flagship product, eGViacoat, as a judge for SEMI’s inaugural Best of the West Award program at SEMICON West 2008. Since then, a combination of strategic planning, a one-of-a-kind technology, and loyal investors has Alchimer poised for take-off even in this stalled economy. I caught up with CEO Steve Lerner on Friday, to find out how it all came together.

While eGViacoat is actually the second product in the Alchimer arsenal of three, the strategic decision to target its promotion first was all about timing. Lerner explained that as TSV metallization processes are still being established, the opportunity exists to assume a leadership position where there is no established process.

“This is going to be a hot wave – better than bumping,” says Lerner. “This is an industry-wide wave affecting both front and back-end processes.” He said the company has recipes for via-first, middle, and last processes, as well as TSV for interposers, different substrates and a whole range of dimensions. “We will evolve with the field and provide solutions for everyone; logic, memory, image sensors…” he said.

Alternatively, Lerner explained that eGSeed, the first product developed based on the company’s electrografting (eG) processes, is a dual damascene process that competes with the more complex, established market currently committed to dry PVD and CVD processes. Lerner is confident that Alchimer’s processes can out-perform dry processes at a fraction of the cost, and it’s simply a matter of time before displacing them. Once eGViacoat’s position is secure, Lerner intends to do just that.

The third product (still in beta) is AquiVia, a wet process for isolation, barrier, and seed layer deposition that picks up where Viacoat leaves off. It allows the same tool to be used for insulation, barrier and seed layer deposition, and completely eliminates dry process techniques from TSV metallization resulting in a 70% cost reduction. “It’s all about cost,” says Lerner about TSV adoption. “Quality and design rules are a given, but the overriding driver is cost.” AquaVia is positioned to launch mid-year, and by SEMICON West 2009, all three products will be promoted as a full-line solution.

In addition to the Best of the West Award, eGViacoat has racked up recognition as finalists in both the 2008 Advanced Packaging Awards, and Eurasia IC Industry Awards, and as a top new product for 2008 by Fabtech.

The company announced its first licensing deal with NEXX Systems, provider of electro-deposition systems for TSV applications, for metallization of high-aspect ration TSVs.
Landing its first user licensee , according to Lerner, was the result of meeting with DALSA Semiconductor’s visionary Luc Ouellet. Ouellet analyzed the MEMS manufacturing process and recognized Alchimer’s value proposition as applied to copper TSVs for the company’s low-cost MEMS products. After successful testing, DALSA decided to license the technology.

Lerner scoffs at statements reverberating currently throughout the industry that the front-end is dead and the back-end will follow. He’s been around awhile, and knows that this is all part of the industry lifecycle. Those who make it through will be the ones who are strategically positioned, offer innovative solutions, and are open to collaboration. The semiconductor phoenix will rise again, and Alchimer will assume an active role.

Oerlikon streamlines for 3D and solar

Oerlikon’s double-barrel news about the sale of its Oerlikon Esec business unit to BESI, and expected management buyout of its etch unit brings to fruition strategic plans I got wind of in October at SEMICON Europa. At that time, Sven Jarby, who heads up marketing and communications for Oerlikon Balzer’s Coating, alluded to the company’s strategic plans to focus on applications that appeal to its core competencies; thin film and coating for TSV processes and solar panels.

By divesting itself of its only traditional back-end semiconductor unit, the wire and die bonder business, Dr. Uwe Krüger, CEO of the Oerlikon Group, says “Oerlikon has significantly reduced its exposure to the cyclical semiconductor market.” It becomes more apparent as companies align themselves vertically that knowing what your company’s core competencies are and focusing on those is a good way to carve a niche in the future of the industry.

The other ponderable question is what BESI will do with Oerlikon Esec’s die bonder division. The organization already holds a strong market position in the die bonder arena with Datacon. According to a press release from BESI, the Esec brand name will be retained, and plans are underway to leverage synergies between the two companies. I'll be curious to find out what becomes of the Oerlikon Esec/Muehlbauer alliance that was announced in November, which was intended to provide turnkey solutions for the smart card module industry. It’s no secret that Datacon is firmly established in RFID technologies. Will this make for strange bedfellows or will it be a merging of the minds? I’ll be keeping my eye on this one.

What's holding up TSV adoption now?

One of the questions plaguing all of us waiting for the adoption of TSVs for 3D IC stacking is what's the hold up? We've been hearing about IT for so long, we're straining forward in our seats ready for take off. But it's complicated. While equipment and material processes have been proven to achieve sub $200/wafer cost, with $150/wafer as the next target, there are still limitations to be addressed, namely EDA tools, thermal management materials and processes, and test.

The quarterly issue of iMicronews' Advanced Packaging Newsletter arrived in my inbox today, and coincidentally two articles shed some light on progress with two of these limitations. Paul Magill's Wanted: Thermal Management Materials for 3D ICs explains Nextreme Thermal Solutions approach for using thermally active copper pillar bumps for acive side, back side and lateral cooling. In Will 3-D EDA Tools be Ready in Time? Sally Cole Johnson queries execs and design engineers at IBM, CEA Leti, R3Logic, and Cadence for answers to that million dollar question. (NOTE: If you're one of those people who gets upset when someone tells them how the book ends, don't read any further.) The conclusion? Mostly smoke and mirrors. All we know for sure is that they're working on it.