Notes from the Exhibition Hall

I have to admit that this year at IMAPS Device Packaging Conference, I spent more time attending technical sessions and less time with the exhibitors than I usually do at an industry event. However, I did manage to check in with a few of them to see what their latest contributions are to the 3D IC and 3D Packaging realm.

Palomar Technologies
I wasn’t surprised to run into Bradley Benton at the Palomar booth – I pretty much expect to see him at these events. In fact, he gave me my first comprehensive lesson in the history of wire bond technologies. I was, however, surprised to learn that the company, which is firmly established in the wire bond business, is venturing into the TSV space with its 6500 Eutectic Die Attach System. Benton says the tool is designed to perform die to wafer processes, and achieves 1.5 µm placement accuracies.

“We recognize that TSV is coming,” he noted. “We have some TSV capabilities now. We’re looking into ways of enhancing that.” Benton says his interest in 3D packaging is why he got into this business 26 years ago. “I always assumed microelectronics would build up and not out.” He said. “What’s new is that we’re finally going at it and doing it with silicon.

SUSS MicroTec
I caught up with Kathy Cook of SUSS MicroTec at the tail end of the poster sessions on Thursday, where she was presenting a poster based on Margarete Zoberbier’s recent presentation at SEMICON Korea about some of SUSS’ equipment technologies for TSVs. Cook explained that polymers adhesives may be necessary for permanent bonding when copper alone isn’t enough to hold the wafers together. The take-away message was the company’s achievement of submicron post bond alignment accuracy (.35µm) for permanent bonding and several other new capabilities involving SUSS’s latest 300mm tools – ACS300 Gen 2 Coater and the MA300 mask aligner. The 300mm permanent bonder is the XBC300. SUSS has recently achieved some excellent results in the area of thin wafer handling as well.

Tango Systems
Martijn Pierik, of Impress PR, introduced me to the folks at Tango Systems, who were showcasing the company’s flagship PVD system, the Axcela. Ravi Mullapudi, president and CEO, explained how the tool was suited to perform barrier and seed layer processes for TSV, which have been identified as areas still to be addressed from a cost of ownership perspective. He said this dry, vacuum process uses rotating targets in the chamber to perform both steps in one process. The tool can accommodate 150, 200 and 300mm wafers, with quick changover.

Surface Technology Systems
In between catching up on non-industry related news, my good friend Michelle Bourke of STS, clued me in on the companies continued work with improved control of TSV profiles. STS has made lots of progress in maintaining the delicate balance between high etch rates and excellent across-wafer etch depth uniformity. One exciting bit of news she shared with me was the company’s recent R& D success with high speed deep reactive ion etch (DRIE) at 106µm/min. While the process needs to be refined, the point is, they’ve achieved it. So expect to see more on this as the process is tweaked. – F.v.T

IMEC’s Latest Contribution to 3DSiP

Last week, at the Smart Systems Integration conference in Brussels IMEC announced it’s latest 3D SiP technology – the ultra-thin chip package (UTCP). The announcement came while I was at the IMAPS Device Packaging Symposium, which was also being attended by Eric Beyne, scientific director of IMEC’s Advanced Packaging and Interconnect Center, so I asked him for some more details.

Beyne told me the process involves embedding a thinned, 25µm die in polymer film to form a 3D structure. At this stage, Beyne said the Known Good Die (KDG) issue can be addressed, because the chip can be tested through the film. The resulting package is a vehicle for embedding either rigid or flex PCB using standard processes. After embedding, other components, such as a Texas Instrument DSP processor or a wireless sensor can be mounted above and below the embedded chip, leading to high-density 3D integration. If the UTCP is embedded in flexible or even stretchable substrate material, it’s ideal for wearable electronics.

Here comes the really cool part. Beyne explained some of the applications this technology is intended for. One is for measuring brain activity, and interest has been expressed by a hospital that performs epileptic analysis in children. It is less invasive than current methods, which, as Beyne put it, requires the patient to be hooked up with all sorts of wires, and then told to “behave normally.” Kind of hard for a child to do, wouldn’t you think? However, with the UTCP technology, a wireless sensor can be embedded into a stretchable substrate that is part of a hat worn by the child, and transmit signals remotely, so the child can certainly behave normally. Beyne says a similar concept could apply to sleep studies.

Beyne also noted that in the scheme of 3D technologies, these low volume biomedical applications would be difficult to achieve using TSV processes, and is another reason why it makes sense to develop embedded technologies as well. Which is why at IMEC, R&D is largely technology driven. “In the end, we need to have applications to fit the technologies,” noted Beyne. – F.v.T

IMAPS Global Business Council and Device Packaging Symposium in Review

Last week’s event s, held back-to-back at the picturesque Fort McDowell Resort and Casino, Scottsdale, AZ, brought together industry experts, vendors, and academia for a week-long full immersion session in the latest developments of microelectronic device packaging.In addition to the exchange of information and ideas, this remote venue offered attendees and exhibitors a chance to network. Here are a few photos I snapped during some of the social events. Kind of makes you wish you were there, doesn’t it?