Another step forward for EDA Tools

I have to admit, I’ve always had difficulty trying to wrap my head around software, especially design tools. So I’ve come to have a deep respect for those individuals charged with the task of designing the design tools themselves. Not only do they need to be able to visualize the end result, they have to work backwards to anticipate the steps required to get there, and then figure out a way to archive that knowledge for later use. In essence, before a design tool can be designed, the methodology of the steps to achieve this must be established. Then, EDA tool designers create a tool based on these established methodologies to be able to automate the design processes for manufacturing.

Current 2D tools have no notion of a 3D hierarchy and thus no way to build IP libraries for 3D. To design 3D ICs, designers had to resort to tricking 2D tools by renaming design layers or creating multiple copies of standard cell libraries. This “design-by-hand” works fine for 2.5D structures like CMOS image sensors and homogenous 3D DRAM memory stacks, but as Lisa McIlrath, of R³Logic, pointed out during the panel discussion at DATE 2009, logic/memory stacks and true heterogeneous integration will need fully functioning 3D design tools.

Understanding the ramifications of this is what makes R³Logic's latest achievement of that much more noteworthy. The company was recently awarded a patent for “methods and systems for computer aided design of 3D integrated circuits”. According to a company statement, the patented invention comprises both the method of defining a 3D technology file that can incorporate one or more 2D wafer technologies corresponding to different tiers in a 3D stack, and that of defining a 3D hierarchical structure for functional blocks within a 3D system. Managing multiple design libraries while properly handling IP blocks that reside on more than one tier is crucial to 3D system design, notes R3Logic, whether at the circuit layout or at the system architecture level.

Achieving this milestone brings th 3D design pioneer another step closer to proving the industry with the tools they’re seeking. I offer my congratulations and look forward to hearing more about it. – F.v.T

3D from all angles at DATE 2009 3D workshop

As I was unable to attend Design Automation Test in Europe (DATE 2009) myself, but felt the information being shared there would be useful to my readers, I asked fellow 3D enthusiast, Yann Guillou, new technology marketing, St Ericsson, if he would write a guest post for “Françoise in 3D”. He graciously agreed, and what follows is his coverage of the event. -- F.v.T

Overview
Nice, in the French Riviera, hosted a hot event on 3D TSV integration in late April. Indeed, one of the Friday workshops of DATE 2009 was dedicated to 3D integration and brought together experts from design, architecture, process, test, and packaging. More than 70 industrial and academic attendees from Europe, Asia and the US attended. In these difficult economic times, it is a proof of the quality of the papers and speakers. Luckily, I had the opportunity to co-chair the event with organizer Erik Jan Marinissen from IMEC and his colleague Geert Van der Plas.

Keynotes
The workshop started with two talks delivered by invited speakers, followed up by 6 papers selected out of 35 submissions, more than 20 posters. A panel discussion with 3D experts concluded this intense day.

Sitaram Arkalgud from Sematech delivered a keynote address on the promises of TSV, and addressed the main technological challenges. He went through all the process steps and options to achieve 3D structures with TSV. Very clear in his explanations, his presentation enabled the test, design, architecture community of DATE to have a global overview of the TSV technology. He showed some cost simulation done by Sematech and stressed that the applications will drive most of the choices. He concluded by sharing results of a survey done by Sematech listing the main challenges of 3D TSV seen by the companies. And surprisingly for some people, the TSV process did not appear to be the most challenging item. 3D design tools and methodologies, thermal management, supply chain definition or test strategy were among the top ranked. Technology was not. He insisted on the need for a roadmap, and again, a roadmap based on the applications. As of today, most of the TSV roadmaps are technology driven, bottom-up roadmaps. He would recommend a top-down assessment from the system driver. That would help in building coherent 3D R&D and getting the critical mass. He concluded by stating TSV was not a single technology element but part of a whole of domains and competencies.

The second invited speaker, Riko Radojcic from Qualcomm, gave some flavors on Qualcomm CAD strategy for 3D TSV. He insisted on what he calls “Pathfinding,” “TechTuning,” and “Design Authoring.” He underlined the thermo-mechanical challenges related to 3D TSV and the new paradigm coming. Difficulties will come from the multi-scale thermo-mechanical analysis that will be required with 3D structures: mm scale at packaging level, µm at chip level, nm scale at transistor level. He added a 2.5D design environment should be enough at the beginning for stacks of dies up to 2. Then, a real 3D environment will be required.

Presentations
Interests of TSV for different applications were presented by both STMicroelectronics and Toshiba for multimedia and multi-core processors. Endicott Interconnect showed some R&D work on advanced substrates with vertical vias (not TSV in that case!), eventual sufficient solutions for particular applications. Georgia Tech presented test solutions for 3D, whereas IMEC presented some results based on the cost model tool they internally developed.

Panel Discussion
Pol Marchal (IMEC) moderated the final panel discussion. Showing 3D TSV samples done at IMEC, he provocatively asked the panelists: “Look, it is possible to make it; we did stack of die with TSV.” He asked them: “Why not tape out products next year?”

Nicolas SIllon (CEA-LETI) gave an overview of LETI latest developments. He announced it will soon be possible to manufacture product with low-density TSV. LETI will be ready for it. Regarding high-density TSV, he added he was wondering if there were today some applications requiring thousands of TSV with diameter of a few microns only.

Paul Siblerud presented EMC3D latest developments and underlined the most critical process steps to make TSVs. He concluded by saying some challenges were existing but none were seen as a show stopper.

Pascal Urard (STMicroelectronics) presented the first products on the market from STMicroelectronics with TSV, the image sensors. He answered the moderator’s question by saying, yes, we can manufacture products with TSV. They are not 3D at IC level today, but they could be in future.

Geert Van der Plas (IMEC) highlighted that the analog and RF community should be more involved in 3D TSV as many improvements could come from this technology.

Krishnendu Chakrabarty (Duke University) gave some insight on test and explained the nice concept of “pretty good die” for 3D.

Finally, Lisa McIlrath (R3Logic) pointed out the fact that CIS or a stack of DRAM with TSV can be designed "by hand" whereas logic/memory or true heterogeneous cannot.

The panel session finished the day on an optimistic note. Let’s solve all these challenges now!

An Electronic Workshop Digest is available for download at the workshop’s web site
Contact Yann Guillou at Yann.Guillou@stericsson.com

Lisa McIlrath, R3 Logic: design tools for 3D IC are on the way

Mea culpa. I may have jumped to conclusions in yesterday’s post. Although it appears to those developing 3D IC integration processes that the design community hasn’t been heeding the call for the much needed design tools, after talking with Lisa McIlrath of R3 Logic, I realized there’s a lot more to it than that. In fact, the message has been heard, but these things are more convoluted than we think. In fact, it's a bit of a cart-before-the-horse situation. How can design tools be developed until the process technologies, characterization, and paramaters have been determined, and prototypes tested? For that matter, each customer is likely to establish its own design rules.

Consider that 3D IC integration is still a very new field, and that everyone is very much in what McIlrath called “pathfinding mode”; exploring different designs before having the parameters figured out. She said that there’s lots of advance work being done to discover different customer needs. Design tools needed now for CMOS image sensors and soon for stacked memory may not necessarily turn out to be the same ones needed down the road for heterogeneous integration. Unfortunately, it’s still not clear what the winning applications will be.

For large companies, there's not much incentive to invest in development until the picture is clearer and the market is big enough. However the buzz is that Cadence has been some internal development, and and Synopsis and Mentor are sending some of their people to Friday’s 3D Integration Workshop at DATE 2009, in Nice, France. Clearly, the interest is growing.

McIlrath said that although it might be risky and difficult for small companies to set a course on a tool that may not be adopted, it’s also easier for them to be agile as the market shifts and changes. For example, R3 Logic discovered a need by the research community for a layout editor, so they partnered with MicroMagic to develop one. (Tezzaron Semiconductors, pioneers in manufacturing stacked memory with TSVs uses the tool, and has endorsed it.) This week at DATE 2009, McIlrath says R3 Logic will be showcasing a 3D floorplanning tool scheduled for install this summer. Additionally, last month, the company announced a collaboration with ST-Microelectronics and CEA-LETI to develop a full 3D design flow.

McIlrath says that although it’s regrettable that there aren’t more tools out there and available, she doesn’t agree that the lack of design solutions, or test for that matter, is a blocking factor in TSV adoption. “3D integration is going to go ahead with or without any particular player,” she said. “The design tools are coming. Our goal is to find the most appropriate tools to suit the needs of the users.” – F.v.T

3D EDA Tools – Coming out of the Woodwork

That didn’t take long. A post about one EDA tool introduction inspired a comment about a 3D layout editor that’s been on the market for 2 years. A mention of said comment in Tuesday’s email update and an email to the individual who posted the comment brought immediate response. This is the beauty of blogging; it results in an almost instantaneous sharing of information and inspires collaboration.

According to Mark Mangum, sales manager for EDA tools and chip design tools at Micro Magic, Inc, the company’s layout editor, MAX 3D, handles the physical design of the chip, and is particularly suited to TSV design. He explained that its ability to manage separate wafer levels with individual tech files is more effective than relying on a "super tech file" to handle the whole design. With this approach, each wafer level maintains its own tech file throughout the design process.There is an additional tech file for the interconnect. In addition, the tool’s speed and capacity is ideal for handling the size and complexity of TSV designs. A slower editor tends to decrease performance drastically.

Three important elements of good EDA tools are programmability, customizability, and compatibility with other tools in the toolbox. Mangum assured me that MAX 3D was developed with these considerations in mind. “Integration is a key selling point for our customers, so we've made an effort to make our tools work with others.” he said, adding that the tool was developed for “open architecture”, with ASCII data files and open source scripting language. OpenAccess support was added for design data files due to customer demand, and is continually updated. To handle Pcell design data, a Pcell interpreter from IPL was added to allows users to read their Pcell data. "MAX-3D has real time design rule checking (DRC), but because many customers use Mentor Calibre for signoff DRC, a direct interface to Calibre was added. We also support industry standard file formats such as GDSII, LEF, DEF, etc. so MAX-3D users won't have to worry about "vendor lock-in" of file formats - for design data, cells, or generators,” he said.

Mangum told me MAX-3D is being used by several universities, including MIT, Lincoln, Cornell, North Carolina State, Penn State. Six companies have also incorporated it into their processes, mainly for developing test chips.

Are there other 3D tools in the works at Micro Magic? Mangum says yes, but is hush-hush about it. "We are working on some packaging-related development with a customer, but no word on when we'll be discussing it," he said. Simulation and verification are big blind spots in the industry right now, he added, but rumor has it, Mentor has something in the works on this.

I know one of Micro Magic’s customers is happy with the performance of the company's tools. An unsolicited endorsement appeared in my inbox shortly after I mentioned the product in my email. Gretchen Patti, technical communications specialist for Tezzaron Semiconductor, stated simply, yet enthusiastically. “About Micro Magic: Their tools are real! We use them.” That’s pretty much all I needed to know. – F.v.T.

EDA Tool Addresses 3D Design Limitations

One by one, it looks like to-do items are being checked off the list of TSV adoption limitations for 3D ICs, and it seems that collaborative efforts are making the most progress in achieving desired consequences. For example, we’ve been hearing the cry for design tools for quite some time, and yesterday Javelin Design Automation, in cooperation with IMEC and Qualcomm, announced a breakthrough with its Pathfinder tool for design exploration and optimization of 3D stacked ICs (3D SIC).

According to a joint statement, The team developed a detailed 3D flow to determine accurate performance/power/cost estimates for a 3D stack. The flow was then validated by using it in a smart phone application. The results demonstrated how using TSVs as the method of interconnect allows for a decrease in power, thereby allowing for an increase of bus-width between microprocessor and memory.

Pol Marchal, principal scientist of IMEC who worked on the project, explained some of the ramifications of this work to me. “The PathFinding tool brings 3D technology one step closer to adoptation as it helps to assess the cost/benefits of 3D technology in the early phases of design.” he said. IDMs hesitate to adopt 3D, he explained, because they don’t understand system benefits. Additionally, he said if they do have ideas, they have no way to determine how their system-level decisions might complicate physical designs. By creating a prototype with this tool, the system design team can obtain valuable insights in the power/performance/cost trade-offs for various 3D integration scenarios. One example of comparing these trade-offs was with IMEC’s studies in 3D WLP vs. 3D SIC.

Additionally, integration and packaging teams can benefit from reviewing the prototypes to address and perhaps eliminate manufacturing challenges 3D stacks pose down the line. For example, Marchal explained, can the envisioned 3D stack be packaged? Can the dissipated power be removed from the stack? Is the stack mechanically reliable? Relying on a prototype rather than a spreadsheet allows for practical and focused discussion, which in turn allows for easier evaluation of alternative integration schemes. “As 3D system-level decisions have such impact on final cost, we believe that physical design prototyping will become an essential step in the 3D design flow,” said Marchal, adding that in addition to the path finding tool, obvious follow-ons will include design authoring and verification tools for 3D place and route, layout, layout versus schematic check / design rule check, extraction, etc.

What’s most interesting to me in this latest achievement, is the demonstration once again of the power of collaboration to bring ideas closer to fruition. In cases like this, everybody wins. Javelin gets to be the first out of the gate with a marketable tool that’s been validated by two reputable organizations. IMEC has access to a tool that could very well catapult forward further research in 3D integration. Qualcomm gets to reap the benefits as an early adopter of 3D technologies in their products. I’d say that’s a pretty good start to the week. – F.v.T.

What's holding up TSV adoption now?

One of the questions plaguing all of us waiting for the adoption of TSVs for 3D IC stacking is what's the hold up? We've been hearing about IT for so long, we're straining forward in our seats ready for take off. But it's complicated. While equipment and material processes have been proven to achieve sub $200/wafer cost, with $150/wafer as the next target, there are still limitations to be addressed, namely EDA tools, thermal management materials and processes, and test.

The quarterly issue of iMicronews' Advanced Packaging Newsletter arrived in my inbox today, and coincidentally two articles shed some light on progress with two of these limitations. Paul Magill's Wanted: Thermal Management Materials for 3D ICs explains Nextreme Thermal Solutions approach for using thermally active copper pillar bumps for acive side, back side and lateral cooling. In Will 3-D EDA Tools be Ready in Time? Sally Cole Johnson queries execs and design engineers at IBM, CEA Leti, R3Logic, and Cadence for answers to that million dollar question. (NOTE: If you're one of those people who gets upset when someone tells them how the book ends, don't read any further.) The conclusion? Mostly smoke and mirrors. All we know for sure is that they're working on it.