Léti and Brewer Science: sharing a common lab and a common goal

With the recent announcement of CEA-Léti and Brewer Science's agreement to create a common lab for further development of 3D stacking processes using Léti’s thin wafer handling processes and Brewer Science, Inc. (BSI) WaferBOND™ materials, I realized although both names popped up frequently in relation to the EMC^3D Consortium, they tend to keep a low profile. An interview was definitely in order to learn more about the roles they play in 3D IC integration developments. Fortunately Andre Rouzaud and Nicolas Sillon of Léti, and Rama Puligadda and Mark Privett of BSI, were available to answer my questions and provide more in-depth information about the collaboration. Here’s what I learned from them.

Léti’s research field in 3D integration is driven by the needs for increasing the density of functions, with an ultimate goal of heterogeneous integration of functions such as RF, logic, memory, MEMS, using a variety of technologies to achieve these processes at a lower cost. Léti develops methods to use short vertical interconnects between stacked dies, specifically involving TSVs. Since a broad spectrum of options must be investigated, it makes sense to form alliances and consortia to help accelerate commercialization of technology.

“The partnership collaborative model we have at Léti is quite special,” explained Rouzaud. “Although open to multi-partner projects (mainly for upstream research), we promote bilateral collaborations with specific identified partners on determined research domains.” Leti’s involvement with EMC3D is an example of a multi-partner project, while the partnership with BSI (also a member of EMC3D) is an example of a bilateral collaboration. In the case of the latter, part of the program involves the establishment of a mid-term common laboratory where a dedicated Léti team works closely with partner assignees (in this case, BSI) in the Léti premises on commonly defined programs that are periodically assessed, adapted, and adjusted through regular Léti/partner steering committees. This flexibility in the common project evolution allows the partner to take into account possible changes in his market environment or in his business strategy.

In the area of temporary bonding and protective materials, Léti is clearly committed with BSI. While the scope of work being done by Leti and BSI goes beyond their affiliation with EMC3D, extending into specific customer projects, Privett noted that information is shared as it relates to the EMC3D goal of developing TSV process at a cost of <$150/wafer. Leti and BSI’s focus in the common lab agreement is in developing standard processes for TSVs. Specifically, they have been working in the area of temporary bonding and protective materials for handling thin wafers. Process development is geared toward either via first or last, die to wafer (D2W) or wafer to wafer (W2W), in the foundry or in the packaging house. Rama says the goal is to be prepared for all scenarios. Although the processes might require slight adaptation, ultimately they can be done either place. “The partner will choose the solution,” she explained. “Temporary bonding and debonding can be used for both chip to wafer and wafer to wafer processes. The silicon still has to go through back grinding and subsequent post-fab processes for either.”

“We feel via last will be adopted before via first, because the first demonstrations with CMOS image sensors have been done with via last, and no adjustments have to be made to front end processes to achieve that.” noted Sillon.

Although the initial common lab agreement between Léti and BSI is set for 3 years, the flexibility of the arrangement allows for it to change as the project evolves. “We are focused together on the roadmap of 3D integration,” noted Rouzaud. “I suspect it will not be done in 3 years.” Privett added that market research(Yole Développment) points to 3D IC integration being in high volume manufacturing by 2015, at which point only 20% of all memory will be manufactured this way (51% wire bonded, 30% discrete). He said that leaves 80% worth of memory still to be addressed. “Hopefully we’ll still be talking about 3D integration in 3 years,” he said. In the mean time, notes Puligadda, “It’s been a wonderful relationship.” – F.v.T.

Sound Bites from IMAPS Global Business Council

Yesterday, a full line up of industry experts offered their perspective of supply chain developments for 3D packaging, in addition to general commentary on what needs to occur to solve current technology limitations. In no particular order, here’s a collection of evocative comments I collected throughout the day.

Jan Vardaman, TechSearch International on TSV programs: Almost everyone has a TSV program. Despite the downturn, people are putting money into the TSV area. People recognize if you don’t put your money in the emerging technologies, you won’t be able to play in that market later.

Bill Bottoms, Nanonexus on the future of wire bond stacking: “We need to get rid of stacked die wire bond assembly. In the future, we can’t afford space, additional inductance, and additional power. Interconnect density will out-run anything we can do with wire bond."

Rosalia Beica, Semitool and EMC3D Consortium on the benefits of partnership: "In order to successfully implement 3D IC technology in the industry , we need a good understanding of the providers of this technology. If we can provide solutions to overcome challenges, it will be easier to implement the technology.”

Eric Beyne, IMEC, on 3D terminology: “There is confusion with 3D terminology . How can we come to a clear roadmap if we don’t have a clear definition of 3D technologies?” and on comparing overall cost of 3D IC development: “We have to be careful with cost comparison. If you look only at the cost of TSV it’s not realistic.”

Bob Patti, Tezzaron, on lessons he’s learned as an early adopter of 3D IC integration: “I’ve been involved in 3D for 10 years, and one thing I’ve learned is that it’s really hard to change this industry.” And on the Evolution of 3D technologies: “I think right now, there are too many choices. In the future there will be more than one, but fewer than today. Reduction to volume practice will pick the winners.”

Jean Trewhella, IBM, on the IDM’s viewpoint of collaboration projects in 3D: “Collaboration allows us to get points of view from many different users, even if IBM is not serving that space, our partners will be.”

Jim Walker, Gartner, on the effect of 3D Integration on the supply chain: 3D and TSV are changing the structure of the semiconductor industry. There’s a change in IC design rules; true system-level design is now possible. The supply chain is restructuring, and the roles of equipment and materials suppliers are being redefined, as front-end equipment manufacturers and material suppliers are getting involved.

Tom Gregorich, VP packaging, Qualcomm on adopting TSV in cell phones: TSV TSS (through silicon stack) Is the most viable next generation technology for cell phone 3D construction.

Leo Linehan, Rohm and Haas, on the material providers perspective of 3D technologies: “These conferences are useful for material scientist to learn about the end-use challenges. We as a material vendor are looking for economy of scale. With TSV, a real opportunity is coming in the future, with stacked memory and on the MPU side. CMOS image sensor, while in high volume, is a relatively small market for us.”

Suresh Gowalker, Intel, on various roles for TSV in future packaging technologies: Processor and memory will require customization as complexities, interdependencies, and performance demands go up. Dedicated thermal TSVs for thermal management, and DRAM TSVs to “feed the beast” (power limitations) are viable options.

Marc Robinson, VCI, on successfully rolling out a new technology in the existing supply chain: “VCI’s key role was to ensure the process integrates seamlessly into the existing supply chain. We had to demonstrate that there wouldn’t be much change to the existing infrastructure. Establishing equipment and material partners helped to convince the supply chain it was ready for adoption.

The three-day Device Packaging Symposium kicked off today, with a full track on developing 3D technologies. So look for continuing coverage, and sound bites from this event later in the week. - F.v.T

The TGIF 3D Buzz

As my first official week blogging about 3D IC packaging technologies winds down, I'm thinking a Friday wrap-up is in order, and should probably become a regular event. (Being a fly-by-the-seat-of-your-pants kind of person, it's only natural that this blog takes shape as the opportunities present themselves, don't you think?)

Trolling the web for 3D info this morning, I unearthed what I consider to be some noteworthy points of interest. First of all, I found out that NEXX Systems has become a member of SEMATECH's 3D Interconnect Program at the University of Albany's College of Nanoscale Science and Engineering. Specifically, the collaboration will focus on developing high-yield, low-cost copper electroplating processes to enable high-density TSVs. Another thumbs-up for the effectiveness of collaboration.

Next, Ziptronix announced it is developing licensing sGtrategies for it's ZiBond low-temperature covalent bonding and DBI direct bond interconnect technologies across the supply chain, because according to CEO Dan Donabedian, each link in the chain including EDA tool venders, equipment manufacturers, OEMS, IDMS, chip manufacturers and foundries, stand to gain something from these processes. Look for an in-depth interview on these developments next week.

Two additions to the event calendar include MEPTEC's Semiconductor Packaging Symposium, which, among other things, touches on latest developments in 3D technologies that have made it to full production: PoP stacks, and TSV for CMOS image sensors; and EMC3D Consortium's Asia Tour, which will focus on latest advancements in 3D integration using TSV technology from trends and roadmaps, to performance requirements, cost-effective applications and more.

And finally, while she says it's not "new" news, Gretchen Patti, of Tezzaron Semiconductors, passed along an interesting paper she penned that's worthy of attention as it touches on an advantage of 3D ICs that I had yet to see listed among the usual laundry list of benefits. Evidently, by nature they offer security benefits in two ways. Due to the layered manufacturing processes, their circuitry is virtually impossibly to decipher during manufacture, and fully assembled 3D ICs defeat reverse engineering. For the full story, download 3D-ICs and Integrated Circuit Security. - F.v.T

3D technology research gets another shot in the arm

It looks like it's 3D to the rescue again. I love it. Yesterday, a collaboration was announced by Semiconductor Research Corp. and Georgia Tech that involves the creation of the Interconnect Packaging Center (IPC). The center will be located at Georgia Tech in the Marcus Nanotechnology Building, and will involve the combined efforts of programs at Georgia Tech, Harvard, The University of Texas at Austin, Iowa State University and Singapore's Nanyang Technological University (NTU).

The goal is to develop interconnects that have improved communication between different chips via packaging while achieving an overall reduced chip footprint. And joy of joys, half of the research will focus on new 3D technologies.

This is the second 3D-focused, industry-academia project operating out of Georgia Tech. The 3D All Silicon System Module (3DASSM) Consortium, set to launch early this year, is a combined effort of Georgia Tech’s Microelectronics Packaging Research Center (PRC), the Fraunhofer IZM, KAIST, and (to date) 14 participating companies. Unlike the new IPC, the focus of this work is on packaging, not 3D ICs, and involves work with silicon interposers, wafer-level packaging, and thin-film embedded components to ultimately integrate the IC, package and board seamlessly.

So while not directly related to the collaboration with SRC and Georgia Tech, it certainly poses some interesting synergies. Rao Tummala must be dancing in the streets.

What's holding up TSV adoption now?

One of the questions plaguing all of us waiting for the adoption of TSVs for 3D IC stacking is what's the hold up? We've been hearing about IT for so long, we're straining forward in our seats ready for take off. But it's complicated. While equipment and material processes have been proven to achieve sub $200/wafer cost, with $150/wafer as the next target, there are still limitations to be addressed, namely EDA tools, thermal management materials and processes, and test.

The quarterly issue of iMicronews' Advanced Packaging Newsletter arrived in my inbox today, and coincidentally two articles shed some light on progress with two of these limitations. Paul Magill's Wanted: Thermal Management Materials for 3D ICs explains Nextreme Thermal Solutions approach for using thermally active copper pillar bumps for acive side, back side and lateral cooling. In Will 3-D EDA Tools be Ready in Time? Sally Cole Johnson queries execs and design engineers at IBM, CEA Leti, R3Logic, and Cadence for answers to that million dollar question. (NOTE: If you're one of those people who gets upset when someone tells them how the book ends, don't read any further.) The conclusion? Mostly smoke and mirrors. All we know for sure is that they're working on it.