Talking the 3D Talk

I was happy to share the 3D stage as a contributing editor in this week’s issue of AP Semi-monthly. In fact, I found Yann Gillou’s guide to 3D vernacular: 3D Lingo-Getting it Straight really helpful for sorting out the differences between 3D configurations at the package and IC levels, and TSV. Gillou and I met last October at SEMICON Europa, where he explained to me how TSV is often identified as a 3D configuration by itself, when it reality, it is what he calls a “techno brick” used to achieve “real” 3D ICs. It was great to read the final article inspired by this conversation. It’s definitely worth the read.

I was also glad to see 3D ASSM’s presentation at Pan Pacific Symoposium in Hawaii get some ink from George Riley in The Riley Report. Only a month and a half away from the official kick-off, over 45 organizations from the industry, academia, and government have rfeportedly put forth efforts through the planning stages. Riley’s column offers a comprehensive look at the challenges to be overcome if the development of this system-on-wafer technology is to succeed. Just in case you missed these articles in the original eNewsletter, I’ve taken the liberty of linking to them from here. - F.v.T.

3D technology research gets another shot in the arm

It looks like it's 3D to the rescue again. I love it. Yesterday, a collaboration was announced by Semiconductor Research Corp. and Georgia Tech that involves the creation of the Interconnect Packaging Center (IPC). The center will be located at Georgia Tech in the Marcus Nanotechnology Building, and will involve the combined efforts of programs at Georgia Tech, Harvard, The University of Texas at Austin, Iowa State University and Singapore's Nanyang Technological University (NTU).

The goal is to develop interconnects that have improved communication between different chips via packaging while achieving an overall reduced chip footprint. And joy of joys, half of the research will focus on new 3D technologies.

This is the second 3D-focused, industry-academia project operating out of Georgia Tech. The 3D All Silicon System Module (3DASSM) Consortium, set to launch early this year, is a combined effort of Georgia Tech’s Microelectronics Packaging Research Center (PRC), the Fraunhofer IZM, KAIST, and (to date) 14 participating companies. Unlike the new IPC, the focus of this work is on packaging, not 3D ICs, and involves work with silicon interposers, wafer-level packaging, and thin-film embedded components to ultimately integrate the IC, package and board seamlessly.

So while not directly related to the collaboration with SRC and Georgia Tech, it certainly poses some interesting synergies. Rao Tummala must be dancing in the streets.