EVG’s partnership with Léti adds a third dimension

As the old saying goes, things usually happen in threes… and in this case 3D. Three years ago, EV Group (EVG) teamed up with Brewer Science, Inc. (BSI) to develop temporary wafer bonding and debonding processes using EVG tools and BSI's materials. Just a few weeks ago, CEA Léti and BSI announced a joint development program (JDP) for temporary wafer bonding and debonding processes to achieve 3D IC integration using TSVs. Last week, EV Group made a similar announcement regarding a JDP with Leti. Just as I suspected, this move completes a 3-way collaboration for accelerating 3D IC integration. I spoke with Nicolas Sillon, head of the laboratory for advanced packaging and 3D integration at Leti; and Stefan Pargfrieder, EVG's business development manager, to get some more details on the arrangement.

According to Sillon, the program with EVG is complementary to what Leti is already working on with BSI. “We’re mixing three competencies: EVG tools, BSI science, and Leti integration schemes,” he said. Pargfrieder concurred, adding that EVG's previous work with BSI developing temporary bonding and debonding processes on their tools proved the best performance using BSI materials. “To have Léti as an industrial R&D partner allows us to make this a mature qualified technology for a broader range of customers.” he added.

In particular, Sillon said that developing 300mm 3D integration wafer processes is the main goal of the program with EVG. From EVG’s perspective, Pargfrieder says the goal is to establish EVG's technology in the market, and learn from partners about tool performance at the early stages of development to better serve the customer. Therefore, the ability to accomplish this using Léti’s research facilities is a benefit.

As all three entities – Léti, BSI, and EVG – are members of the EMC^3D Consortium, I was curious if this work also tied into that organization. According to both Sillon and Pargfrieder, information will be shared only in as much as can be made public. Sillon says the JDP with both EVG and BSI allows Leti to go deeper into development than they can with EMC^3D . Pargfrieder added that some of the information might be useful to EMC^3D, while some must remain confidential for customer projects.

To learn more about this triad’s work, be sure to catch their presentation on at ECTC 2009, which takes place May 27-29 in San Diego, CA. The topic discussed will be Leti’s via-last application on thin wafers using BSI’s science on EVG’s tool. It looks like the power of 3 is catching on in more ways than one. – F.v.T.

Setting the record straight on TMV and TSV

After attending Curtis Zwenger’s presentation introducing Amkor’s latest contribution to the package-on-package (PoP) family based on the company’s proprietary through mold via (TMV) technology, I feel compelled to correct some misinformation I read last week on a colleague’s blog.

Although TMV appears to borrow conceptually from TSV technology, it is by no means meant to be an alternative technology to TSV. In fact, the two technologies address 3D stacking at different levels, and were developed to address different issues. TMVPoP is a 3D package configuration, and the technology was developed to address PoP warpage issues, overall package size, improve fine-pitch stacking and improved density and signal integrity at the package level. On the other hand, TSV is a 3D IC integration building block for stacking the chips themselves to improve performance, form factor, and signal process packing density. And according to Eric Beyne of IMEC, high density TSV solutions will ultimately be required to optimize system partitioning.

In actuality, according to Lee Smith of Amkor, not only is TMV NOT an alternative to TSV, it was designed to support TSV stacked chips in its bottom package, in addition to flip chip and wire bond designs. I hope this helps clear up any confusion.

Zwenger’s presentation shared data proving TMV’s PoP benefits such as demonstrating the smallest warpage at 25 and 260°. TMV flattens out the package at the corners and improves fine pitch stacking. As a result, when compared to bare die flip chip POP, lower warpage with TMV enables substrate thickness and PoP stack up reductions. Additionally, improved design rules allow for increased die size by 30%. Zwenger also said TMVPOP meets package requirements for high density and signal integrity.

The Device Packaging Symposium has just concluded for the year, but as I suspected it supplied me with enough material to write about for days. So there’s more to come. – F.v.T.

3D EDA Tools – Coming out of the Woodwork

That didn’t take long. A post about one EDA tool introduction inspired a comment about a 3D layout editor that’s been on the market for 2 years. A mention of said comment in Tuesday’s email update and an email to the individual who posted the comment brought immediate response. This is the beauty of blogging; it results in an almost instantaneous sharing of information and inspires collaboration.

According to Mark Mangum, sales manager for EDA tools and chip design tools at Micro Magic, Inc, the company’s layout editor, MAX 3D, handles the physical design of the chip, and is particularly suited to TSV design. He explained that its ability to manage separate wafer levels with individual tech files is more effective than relying on a "super tech file" to handle the whole design. With this approach, each wafer level maintains its own tech file throughout the design process.There is an additional tech file for the interconnect. In addition, the tool’s speed and capacity is ideal for handling the size and complexity of TSV designs. A slower editor tends to decrease performance drastically.

Three important elements of good EDA tools are programmability, customizability, and compatibility with other tools in the toolbox. Mangum assured me that MAX 3D was developed with these considerations in mind. “Integration is a key selling point for our customers, so we've made an effort to make our tools work with others.” he said, adding that the tool was developed for “open architecture”, with ASCII data files and open source scripting language. OpenAccess support was added for design data files due to customer demand, and is continually updated. To handle Pcell design data, a Pcell interpreter from IPL was added to allows users to read their Pcell data. "MAX-3D has real time design rule checking (DRC), but because many customers use Mentor Calibre for signoff DRC, a direct interface to Calibre was added. We also support industry standard file formats such as GDSII, LEF, DEF, etc. so MAX-3D users won't have to worry about "vendor lock-in" of file formats - for design data, cells, or generators,” he said.

Mangum told me MAX-3D is being used by several universities, including MIT, Lincoln, Cornell, North Carolina State, Penn State. Six companies have also incorporated it into their processes, mainly for developing test chips.

Are there other 3D tools in the works at Micro Magic? Mangum says yes, but is hush-hush about it. "We are working on some packaging-related development with a customer, but no word on when we'll be discussing it," he said. Simulation and verification are big blind spots in the industry right now, he added, but rumor has it, Mentor has something in the works on this.

I know one of Micro Magic’s customers is happy with the performance of the company's tools. An unsolicited endorsement appeared in my inbox shortly after I mentioned the product in my email. Gretchen Patti, technical communications specialist for Tezzaron Semiconductor, stated simply, yet enthusiastically. “About Micro Magic: Their tools are real! We use them.” That’s pretty much all I needed to know. – F.v.T.