TSVs: just the tip of the 3D ICeberg

At ECTC last week, I counted at least 21 presentations dedicated to TSVs alone, and 13 dedicated to other processes for 3D IC integration. The sheer volume and depth of research required around bringing these technologies to market is sometimes lost on those of us who sit outside the circle of academia and research, and only hear about those that make it to marketability. And although TSVs have become the poster child for 3D IC integration, sometimes we forget that there are other steps of equal importance to achieving these 3D stacks; namely backgrinding, thinning and dicing; temporary bonding and debonding for both wafer-to-wafer (W2W) chip-to-wafer processes (C2W); and chip stacking.

According to IMEC’s Eric Beyne, while many companies are involved in developing materials and equipment for TSV processes (etch, seed layer, fill, etc.) there are only 2 equipment manufacturers (EV Group and SUSS MicroTec) that offer tools for temporary bonding and debonding processes, and only a few materials companies (Brewer Science, 3M, and Dupont) developing temporary bonding materials. Beyne described one temporary bonding material that when heated, allows the device wafer to slide apart from the carrier wafer; and another that vaporizes the material holding them together. Unfortunately, both of these materials involves high temperatures, which, when used in sequential processes to achieve multiple chip stacks, can stress the ultrathin device wafers. Therefore, IMEC is working on a parallel process to overcome address this. One approach is to stack the chips using a sort of stencil to maintain alignment, and then perform the bond step all at once.

Chip stacking is another step still requiring some solutions in C2W processes, where the perfect combination of speed and accuracy is yet to be achieved. S.E.T has developed a high-precision, flexible die bonder that reportedly achieves a throughput of 150pph, earning the company installs at IMEC, SEMATECH and CEA-Leti; but according to Mike Thompson, CTO of Replisaurus, S.E.T’s parent company, that number needs another zero (1500) to make it volume-production-capable. Solving this alignment plus throughput conundrum is the focus of TNO’s Bluebird project with Datacon. As part of the EMC3D consortium, EV Group is also working with Datacon to solve the C2W stacking issue.

What’s not being revealed is likely to be more important than what is being revealed. As was pointed out to me on more than one occasion last week, companies aren’t likely to talk about what they’re working on until it’s a done deal. And they never talk about what they’ve tried that has failed, which could ultimately be as useful for competitors to know about as the successes are. In any case, it appears that there’s still work to do before all the stars align. – F.v.T.

Live from San Diego, it’s ECTC 2009

When I attend a conference like ECTC, packed with densely detailed technical presentations, I realize just how much work has to happen behind the scenes to bring all these technologies to production. The devil is clearly in the details. In the 3D space alone, there were dozens of papers and posters being presented from across the spectrum of university and research organizations, although proving possible in laboratory settings, many of the processes being discussed will likely never see the light of day in volume production, while others will provide the Eureka moments we’ve all been waiting for. However all of this work is critical to the ultimate mainstreaming of processes, and subsequent development of standards.

As Toshiaki Itabashi of Dupont WLP Solutions, explained to me while leading me through his poster session, Integrated Materials Enabling TSV/3D-TSV, thousands of man hours go into to developing these processes and perfecting the materials. Once the right recipe is achieved, it makes sense for it to become standard going forward.

I had one of those Eureka moments listening to Juergen Leib, research consultant to AAC Microtec, describe a silicon interposer with TSV developed for a space application. For this application, he said the decision was made to merely line a TSV with copper, rather than fill it. Lining it is all that’s required to achieve electrical conductivity, and reduces the potential stress put on the silicon by filling the via with copper. Additonally, the potential for delamination is reduced. “Wait a minute,” I asked. “If it’s not necessary to fill the via, why do it?” Both Leib and Eric Beyne of IMEC provided the answer. It all depends on the application and the diameter of the via. Beyne explained that for vias smaller than 25µm, filling is necessary because lining only can create voids. Another reason to fill is in stacking chips, which requires a microbump on top of each via. In that case, you need to fill to create the bump. But other TSV applications, lining the via is sufficient, and may ultimately create a stronger structure. So there you have it. I learn something new every day. – F.v.T.