Léti and Brewer Science: sharing a common lab and a common goal

With the recent announcement of CEA-Léti and Brewer Science's agreement to create a common lab for further development of 3D stacking processes using Léti’s thin wafer handling processes and Brewer Science, Inc. (BSI) WaferBOND™ materials, I realized although both names popped up frequently in relation to the EMC^3D Consortium, they tend to keep a low profile. An interview was definitely in order to learn more about the roles they play in 3D IC integration developments. Fortunately Andre Rouzaud and Nicolas Sillon of Léti, and Rama Puligadda and Mark Privett of BSI, were available to answer my questions and provide more in-depth information about the collaboration. Here’s what I learned from them.

Léti’s research field in 3D integration is driven by the needs for increasing the density of functions, with an ultimate goal of heterogeneous integration of functions such as RF, logic, memory, MEMS, using a variety of technologies to achieve these processes at a lower cost. Léti develops methods to use short vertical interconnects between stacked dies, specifically involving TSVs. Since a broad spectrum of options must be investigated, it makes sense to form alliances and consortia to help accelerate commercialization of technology.

“The partnership collaborative model we have at Léti is quite special,” explained Rouzaud. “Although open to multi-partner projects (mainly for upstream research), we promote bilateral collaborations with specific identified partners on determined research domains.” Leti’s involvement with EMC3D is an example of a multi-partner project, while the partnership with BSI (also a member of EMC3D) is an example of a bilateral collaboration. In the case of the latter, part of the program involves the establishment of a mid-term common laboratory where a dedicated Léti team works closely with partner assignees (in this case, BSI) in the Léti premises on commonly defined programs that are periodically assessed, adapted, and adjusted through regular Léti/partner steering committees. This flexibility in the common project evolution allows the partner to take into account possible changes in his market environment or in his business strategy.

In the area of temporary bonding and protective materials, Léti is clearly committed with BSI. While the scope of work being done by Leti and BSI goes beyond their affiliation with EMC3D, extending into specific customer projects, Privett noted that information is shared as it relates to the EMC3D goal of developing TSV process at a cost of <$150/wafer. Leti and BSI’s focus in the common lab agreement is in developing standard processes for TSVs. Specifically, they have been working in the area of temporary bonding and protective materials for handling thin wafers. Process development is geared toward either via first or last, die to wafer (D2W) or wafer to wafer (W2W), in the foundry or in the packaging house. Rama says the goal is to be prepared for all scenarios. Although the processes might require slight adaptation, ultimately they can be done either place. “The partner will choose the solution,” she explained. “Temporary bonding and debonding can be used for both chip to wafer and wafer to wafer processes. The silicon still has to go through back grinding and subsequent post-fab processes for either.”

“We feel via last will be adopted before via first, because the first demonstrations with CMOS image sensors have been done with via last, and no adjustments have to be made to front end processes to achieve that.” noted Sillon.

Although the initial common lab agreement between Léti and BSI is set for 3 years, the flexibility of the arrangement allows for it to change as the project evolves. “We are focused together on the roadmap of 3D integration,” noted Rouzaud. “I suspect it will not be done in 3 years.” Privett added that market research(Yole Développment) points to 3D IC integration being in high volume manufacturing by 2015, at which point only 20% of all memory will be manufactured this way (51% wire bonded, 30% discrete). He said that leaves 80% worth of memory still to be addressed. “Hopefully we’ll still be talking about 3D integration in 3 years,” he said. In the mean time, notes Puligadda, “It’s been a wonderful relationship.” – F.v.T.

Notes from the Exhibition Hall

I have to admit that this year at IMAPS Device Packaging Conference, I spent more time attending technical sessions and less time with the exhibitors than I usually do at an industry event. However, I did manage to check in with a few of them to see what their latest contributions are to the 3D IC and 3D Packaging realm.

Palomar Technologies
I wasn’t surprised to run into Bradley Benton at the Palomar booth – I pretty much expect to see him at these events. In fact, he gave me my first comprehensive lesson in the history of wire bond technologies. I was, however, surprised to learn that the company, which is firmly established in the wire bond business, is venturing into the TSV space with its 6500 Eutectic Die Attach System. Benton says the tool is designed to perform die to wafer processes, and achieves 1.5 µm placement accuracies.

“We recognize that TSV is coming,” he noted. “We have some TSV capabilities now. We’re looking into ways of enhancing that.” Benton says his interest in 3D packaging is why he got into this business 26 years ago. “I always assumed microelectronics would build up and not out.” He said. “What’s new is that we’re finally going at it and doing it with silicon.

SUSS MicroTec
I caught up with Kathy Cook of SUSS MicroTec at the tail end of the poster sessions on Thursday, where she was presenting a poster based on Margarete Zoberbier’s recent presentation at SEMICON Korea about some of SUSS’ equipment technologies for TSVs. Cook explained that polymers adhesives may be necessary for permanent bonding when copper alone isn’t enough to hold the wafers together. The take-away message was the company’s achievement of submicron post bond alignment accuracy (.35µm) for permanent bonding and several other new capabilities involving SUSS’s latest 300mm tools – ACS300 Gen 2 Coater and the MA300 mask aligner. The 300mm permanent bonder is the XBC300. SUSS has recently achieved some excellent results in the area of thin wafer handling as well.

Tango Systems
Martijn Pierik, of Impress PR, introduced me to the folks at Tango Systems, who were showcasing the company’s flagship PVD system, the Axcela. Ravi Mullapudi, president and CEO, explained how the tool was suited to perform barrier and seed layer processes for TSV, which have been identified as areas still to be addressed from a cost of ownership perspective. He said this dry, vacuum process uses rotating targets in the chamber to perform both steps in one process. The tool can accommodate 150, 200 and 300mm wafers, with quick changover.

Surface Technology Systems
In between catching up on non-industry related news, my good friend Michelle Bourke of STS, clued me in on the companies continued work with improved control of TSV profiles. STS has made lots of progress in maintaining the delicate balance between high etch rates and excellent across-wafer etch depth uniformity. One exciting bit of news she shared with me was the company’s recent R& D success with high speed deep reactive ion etch (DRIE) at 106µm/min. While the process needs to be refined, the point is, they’ve achieved it. So expect to see more on this as the process is tweaked. – F.v.T

IMEC’s Latest Contribution to 3DSiP

Last week, at the Smart Systems Integration conference in Brussels IMEC announced it’s latest 3D SiP technology – the ultra-thin chip package (UTCP). The announcement came while I was at the IMAPS Device Packaging Symposium, which was also being attended by Eric Beyne, scientific director of IMEC’s Advanced Packaging and Interconnect Center, so I asked him for some more details.

Beyne told me the process involves embedding a thinned, 25µm die in polymer film to form a 3D structure. At this stage, Beyne said the Known Good Die (KDG) issue can be addressed, because the chip can be tested through the film. The resulting package is a vehicle for embedding either rigid or flex PCB using standard processes. After embedding, other components, such as a Texas Instrument DSP processor or a wireless sensor can be mounted above and below the embedded chip, leading to high-density 3D integration. If the UTCP is embedded in flexible or even stretchable substrate material, it’s ideal for wearable electronics.

Here comes the really cool part. Beyne explained some of the applications this technology is intended for. One is for measuring brain activity, and interest has been expressed by a hospital that performs epileptic analysis in children. It is less invasive than current methods, which, as Beyne put it, requires the patient to be hooked up with all sorts of wires, and then told to “behave normally.” Kind of hard for a child to do, wouldn’t you think? However, with the UTCP technology, a wireless sensor can be embedded into a stretchable substrate that is part of a hat worn by the child, and transmit signals remotely, so the child can certainly behave normally. Beyne says a similar concept could apply to sleep studies.

Beyne also noted that in the scheme of 3D technologies, these low volume biomedical applications would be difficult to achieve using TSV processes, and is another reason why it makes sense to develop embedded technologies as well. Which is why at IMEC, R&D is largely technology driven. “In the end, we need to have applications to fit the technologies,” noted Beyne. – F.v.T

IMAPS Global Business Council and Device Packaging Symposium in Review

Last week’s event s, held back-to-back at the picturesque Fort McDowell Resort and Casino, Scottsdale, AZ, brought together industry experts, vendors, and academia for a week-long full immersion session in the latest developments of microelectronic device packaging.In addition to the exchange of information and ideas, this remote venue offered attendees and exhibitors a chance to network. Here are a few photos I snapped during some of the social events. Kind of makes you wish you were there, doesn’t it?

Setting the record straight on TMV and TSV

After attending Curtis Zwenger’s presentation introducing Amkor’s latest contribution to the package-on-package (PoP) family based on the company’s proprietary through mold via (TMV) technology, I feel compelled to correct some misinformation I read last week on a colleague’s blog.

Although TMV appears to borrow conceptually from TSV technology, it is by no means meant to be an alternative technology to TSV. In fact, the two technologies address 3D stacking at different levels, and were developed to address different issues. TMVPoP is a 3D package configuration, and the technology was developed to address PoP warpage issues, overall package size, improve fine-pitch stacking and improved density and signal integrity at the package level. On the other hand, TSV is a 3D IC integration building block for stacking the chips themselves to improve performance, form factor, and signal process packing density. And according to Eric Beyne of IMEC, high density TSV solutions will ultimately be required to optimize system partitioning.

In actuality, according to Lee Smith of Amkor, not only is TMV NOT an alternative to TSV, it was designed to support TSV stacked chips in its bottom package, in addition to flip chip and wire bond designs. I hope this helps clear up any confusion.

Zwenger’s presentation shared data proving TMV’s PoP benefits such as demonstrating the smallest warpage at 25 and 260°. TMV flattens out the package at the corners and improves fine pitch stacking. As a result, when compared to bare die flip chip POP, lower warpage with TMV enables substrate thickness and PoP stack up reductions. Additionally, improved design rules allow for increased die size by 30%. Zwenger also said TMVPOP meets package requirements for high density and signal integrity.

The Device Packaging Symposium has just concluded for the year, but as I suspected it supplied me with enough material to write about for days. So there’s more to come. – F.v.T.

From the DPC: Panelists address burning questions for 3D IC integration

I’m glad I stuck around last evening for the 3D panel discussion on the status of 3D integration technologies, applications and roadmaps. As moderator Phil Garrou pointed out, it offered the opportunity to hear some commentary I might have otherwise missed by only attending the scheduled presentations. As a result, I, and a roomful of active participants, got a peek at the inside track of what’s happening .

Panelists included Bob Patti, of memory-maker Tezzaron Semiconductor; Eric Beyne, director of advanced packaging technologies at IMEC; renowned market analyst and keynoter, Jan Vardaman, of TechSearch international; C.J. Berry, of Amkor product development; and Bioh Kim, director of business development for EV Group. Garrou posed a line-up statements and asked the panelists if they agreed or disagreed, and why. Here’s what the panelists had to say.

In order of appearance, the three short term product drivers — CMOS Image sensors, memory on logic, and memory stacks — are paving the way for the ultimate goal, which is repartitioning. Repartitioning involves dividing chips into functions, producing them on separate wafers and stacking them. Do you agree that this is the ultimate goal?

With regard to the order of release, there was general consensus among the panelists. Vardaman elaborated her position on memory, saying she was “sticking to her guns” that DRAM memory will come before Flash memory due to the cost of TSVs. “Solid state drive makers don’t have it on their horizon, so we know it’s further out there. Berry offered that TSV is about evolutionary steps, and will require a mature supply chain to bring it to market.

Addressing partitioning as the ultimate goal, Patti said that it all depended on the value proposition, and Berry concurred, adding that there was no simple answer to that. Beyne said that memory on logic will lead the way to repartitioning. For memory stacking alone, wire bonding is still the cheapest way to go. He added that 3D partitioning is really a different type of 3D where you’re adding blocks. “It’s a different study involving higher density and is not the same TSV technology, However, at that level, potential cost advantages and paybacks are higher,” he said.

A comment on the floor about seeing “the same pictures as last year” sparked the question, what has changed in a year? Vardaman responded that since last march, a number of companies now offer chip-on-chip solution, which is the step before TSV. Some of the probe card companies — Formfactor, Wentworth Labs, Cascade Microtec —have been working on their probe card technologies; thermal area is showing promise; and some of the small design tool companies like R3Logic have made progress “I think you’re seeing the same pictures because people are still working on this, and aren’t ready to go public with their findings yet,” she added.

Beyne said that in Europe, 3D processes are showing up in MEMS applications and in automotive applications. He also said that a better response from EDA vendors with regard to the EDA issues is a good sign that things are coming because they don’t do anything until things are ready.

“If you’re talking about taking something from first article demonstration to high-volume production, seeing the same picture for a few years shouldn’t shock anybody." added Berry.

Beginning with the adoption of TSV for CMOS image sensors, and memory on logic in the 2008-2009 time frame, followed by backside illumination (BSI) in ’09, DRAM around 2010, and heterogeneous integration and repartitioning by 2014, Garrou asked if the panelist agree with this sequence if not these dates?

Berry agreed with the order, but also suggested that we might see some derivatives of heterogeneous integration by 2012 or 2013, with logic deconstructed on an interposer, for example. “ I wouldn’t be surprised if to see a simplified version of the heterogeneous integration show up a year earlier.” He said.

Vardaman said that other than image sensors, things have shifted out a bit due to the economic condition. “How long does it take to put a 300mm line in? Capex doesn’t look good.” She pointed out.

While agreeing with the sequence, Beyne noted that the image being used on various presentation to depict heterogenous integration “gives a completely false impression of what will happen. It will be a simpler version,” he noted, adding that it’s a question of added value. The driver from business point of view will be the advantage to “fab lite” manufacturers.
Garrou concurred, pointing out that the ability to do this in parts does have an advantage, especially from an IP perspective.

Patti said he agrees with the order of the way things will happen, and also sees it as a good time frame. “I agree flash will be behind DRAM, but phase-change memory will be before flash.” He explained that as phase-change memory is still in the design phase, it offers the opportunity to start from scratch. There’s no hurry to convert existing products to TSV, but when you’re starting with a new memory architecture, and have a problem that can be solved, it makes sense to incorporate TSV.

TSMC stepped forward with a roadmap to do TSV at 50µm pitch – willing to implement in 2011. Will TSMC hold to this roadmap or push out the iTSV production capability?

The consensus among the panel — TSMC will likely push it out. “There aren’t enough customer to justify it, so I think it will push out." noted Patti. “I’ve good reason to believe it’s likely to move because they’re demand driven. There would have to be strong customer demand.”

Berry noted that it’s a difficult business model for TSMC. “Its everyone’s best interest to wait." he said. “It’s always better to delay."

Do we all agree that for the most part, TSV will be a Fab/Foundry business?

While it seemed clear from the panel responses that the vias themselves will be created first in the foundry, who would take ownership of the post fab processes still remains to be seen. Barry said that it’s a question of risk mitigation. OSATS will be in good position to support middle end technologies.

Patti said that wherever it is, it will be important that it’s one entity that’s doing all the post-fab processes in one spot: backside grinding, surface treatment, RDL , microbump, die stacking, assembly and test. He added that since foundries got burned in the bumping business, he sees the task being taken on by the OSAT providers — albeit by a short list of OSATS who can do it.

Offering a perspective from equipment manufacturers, Kim pointed out that transferring very thin, delicate wafers between locations is a concern. “I’m not sure who will be the ones to do it,” he said, “but multiple processes done on very thin wafers, should be done at one location.”

Aside from test, do we all agree that equipment sets are ready for production?

The general concensus among panelists was that yes, with a few modifications in some areas equipment is ready. “EVG is definitely ready.” said Kim.

From the floor, Ted Tessier of Flip Chip International pointed out that there’s still work to be done in the die placement area. “It’s not cost effective yet," he noted.

Design and Test: what is the hesitancy of Cadence and Mentor Graphics to addess the design tool issue, and should it be done under a consortium umbrella?

There was general agreement among the panel that a the design community doesn’t really lend itself to a consortium format. Vardaman observed that with regard to Cadence and Mentor, it is likely they are waiting for a small start-up company to develop the tools, and then they’ll acquire them.

Speaking from his position as an early adopter, Patti said that designs for memory can be done with existing tools. “We don’t like it, it’s a lot of heavy lifting, but it can be done,” he said. However, it will be a problem when it comes to heterogeneous integration. The bigger companies don’t have a compelling reason to develop them yet, Patti added, because they aren’t losing business to a competitor by not having a 3D solution. He named R3Logic and Micro Magic as two small design houses that currently have EDA tools for 3D.

Test – is this being done and kept under wraps?

Test was one of the most elusive areas, with the least amount of response among the panel and audience alike. Patti said he’s not sure how a wafer with 1.5M channels will ever be tested. He offered Tezzaron’s solution of built in self-testing and self –repair. Ultimately, he said, you’ll need to test the final package. “Tera-computing will require self test and self repair." he added.

Approaches to testing memory and logic are completely different, said Beyne. He suggested that inspection is a more viable approach, such as with metrology tools. “A lot of metrology issues can be measured to compliment the testing." In the end, the final structure will need to be tested.

All in all, some direct answers to some fairly provocative questions. As panel discussions go, I’d say this one brought some interesting information to the forefront. If anyone who attended thinks I left something out, be sure to add your comments here. – F.v.T.

Sound Bites from IMAPS Global Business Council

Yesterday, a full line up of industry experts offered their perspective of supply chain developments for 3D packaging, in addition to general commentary on what needs to occur to solve current technology limitations. In no particular order, here’s a collection of evocative comments I collected throughout the day.

Jan Vardaman, TechSearch International on TSV programs: Almost everyone has a TSV program. Despite the downturn, people are putting money into the TSV area. People recognize if you don’t put your money in the emerging technologies, you won’t be able to play in that market later.

Bill Bottoms, Nanonexus on the future of wire bond stacking: “We need to get rid of stacked die wire bond assembly. In the future, we can’t afford space, additional inductance, and additional power. Interconnect density will out-run anything we can do with wire bond."

Rosalia Beica, Semitool and EMC3D Consortium on the benefits of partnership: "In order to successfully implement 3D IC technology in the industry , we need a good understanding of the providers of this technology. If we can provide solutions to overcome challenges, it will be easier to implement the technology.”

Eric Beyne, IMEC, on 3D terminology: “There is confusion with 3D terminology . How can we come to a clear roadmap if we don’t have a clear definition of 3D technologies?” and on comparing overall cost of 3D IC development: “We have to be careful with cost comparison. If you look only at the cost of TSV it’s not realistic.”

Bob Patti, Tezzaron, on lessons he’s learned as an early adopter of 3D IC integration: “I’ve been involved in 3D for 10 years, and one thing I’ve learned is that it’s really hard to change this industry.” And on the Evolution of 3D technologies: “I think right now, there are too many choices. In the future there will be more than one, but fewer than today. Reduction to volume practice will pick the winners.”

Jean Trewhella, IBM, on the IDM’s viewpoint of collaboration projects in 3D: “Collaboration allows us to get points of view from many different users, even if IBM is not serving that space, our partners will be.”

Jim Walker, Gartner, on the effect of 3D Integration on the supply chain: 3D and TSV are changing the structure of the semiconductor industry. There’s a change in IC design rules; true system-level design is now possible. The supply chain is restructuring, and the roles of equipment and materials suppliers are being redefined, as front-end equipment manufacturers and material suppliers are getting involved.

Tom Gregorich, VP packaging, Qualcomm on adopting TSV in cell phones: TSV TSS (through silicon stack) Is the most viable next generation technology for cell phone 3D construction.

Leo Linehan, Rohm and Haas, on the material providers perspective of 3D technologies: “These conferences are useful for material scientist to learn about the end-use challenges. We as a material vendor are looking for economy of scale. With TSV, a real opportunity is coming in the future, with stacked memory and on the MPU side. CMOS image sensor, while in high volume, is a relatively small market for us.”

Suresh Gowalker, Intel, on various roles for TSV in future packaging technologies: Processor and memory will require customization as complexities, interdependencies, and performance demands go up. Dedicated thermal TSVs for thermal management, and DRAM TSVs to “feed the beast” (power limitations) are viable options.

Marc Robinson, VCI, on successfully rolling out a new technology in the existing supply chain: “VCI’s key role was to ensure the process integrates seamlessly into the existing supply chain. We had to demonstrate that there wouldn’t be much change to the existing infrastructure. Establishing equipment and material partners helped to convince the supply chain it was ready for adoption.

The three-day Device Packaging Symposium kicked off today, with a full track on developing 3D technologies. So look for continuing coverage, and sound bites from this event later in the week. - F.v.T