DATE 2009 Addresses Design for 3D Integration

It looks as though the call is finally being heard. Those deeply involved in 3D IC Integration using through silicon vias (TSV) as a method of interconnect have been banging these particular drums and sending up smoke signals to the design and test communities for quite some time now with the same message: WE NEED DESIGN SOLUTIONS and WE NEED METHODS FOR TEST.

During the 3D Panel held last month at IMAPS Device Packaging Symposium, panelists and attendees alike speculated about the why’s and wherefores of the logjam for both; but no one could really come up with a concrete answer. While several smaller EDA vendors were acknowledged for having developed tools for 3D IC design (Javelin Design Automation, MicroMagic, and R3 Logic), the question of when “the big guys” (Mentor and Cadence) would jump on board. The collective assumption is that until TSV is closer to market adoption, there’s no real need for the larger design houses to jump into the ring. Test for TSV is still very much an enigma.

Therefore, it was with delight that I reviewed the agenda for Friday’s workshop at DATE 2009, 3D Integration – Technology, Architecture, Design, Automation and Test. Workshop organizers, Yann Gillou, of ST Ericcson, and Erik Jan Marinissen and Geert Van der Plas, both from IMEC; have assembled a line-up for attendees from the design and test communities designed to educate attendees about the critical need for solutions, and to spark interaction between researchers, practitioners, and others interested in 3D IC Integration.

Session 1, moderated by Lisa McIlrath of R3 Logic, kicks off with a keyote addressby Sitaram Arkalgud, of SEMATECH, titled The Promise of Through-Silicon Vias, followed by invited speaker, Riko Radojcic from Qualcomm, who will outline requirements for the design-for-3D environment. The talk will focus on the design environment and EDA tools necessary for what Qualcomm identifies as the ‘Stage 1’ class of products, consisting of a functionally partitioned two-die stack. He will identify three classes of methodologies and associated EDA technologies.

The rest of the day addresses the gamut of issues surrounding design and test, ranging from power integrity issues and bandwidth optimization, to SOC test architecture, test strategies for 3D IC, and much more. In addition to live presentations and 22 poster sessions, the day will conclude with a panel discussion, The Future of 3D Integration From All Angles, moderated by Peter Ramm, of the Fraunhofer Institute. Panelists include Roger Carpenter, Javelin Design Automation; Krishnendu Chakrabarty, Duke University; Paul Siblerud, Semitool; Nicolas Sillon; CEA-LETI; Pascal Urard, ST Microelectronics; and Geert Van der Plas, IMEC.

They may not have the answers yet, but at least they’re getting the message. It’s a start. -- F.v.T

From the DPC: Panelists address burning questions for 3D IC integration

I’m glad I stuck around last evening for the 3D panel discussion on the status of 3D integration technologies, applications and roadmaps. As moderator Phil Garrou pointed out, it offered the opportunity to hear some commentary I might have otherwise missed by only attending the scheduled presentations. As a result, I, and a roomful of active participants, got a peek at the inside track of what’s happening .

Panelists included Bob Patti, of memory-maker Tezzaron Semiconductor; Eric Beyne, director of advanced packaging technologies at IMEC; renowned market analyst and keynoter, Jan Vardaman, of TechSearch international; C.J. Berry, of Amkor product development; and Bioh Kim, director of business development for EV Group. Garrou posed a line-up statements and asked the panelists if they agreed or disagreed, and why. Here’s what the panelists had to say.

In order of appearance, the three short term product drivers — CMOS Image sensors, memory on logic, and memory stacks — are paving the way for the ultimate goal, which is repartitioning. Repartitioning involves dividing chips into functions, producing them on separate wafers and stacking them. Do you agree that this is the ultimate goal?

With regard to the order of release, there was general consensus among the panelists. Vardaman elaborated her position on memory, saying she was “sticking to her guns” that DRAM memory will come before Flash memory due to the cost of TSVs. “Solid state drive makers don’t have it on their horizon, so we know it’s further out there. Berry offered that TSV is about evolutionary steps, and will require a mature supply chain to bring it to market.

Addressing partitioning as the ultimate goal, Patti said that it all depended on the value proposition, and Berry concurred, adding that there was no simple answer to that. Beyne said that memory on logic will lead the way to repartitioning. For memory stacking alone, wire bonding is still the cheapest way to go. He added that 3D partitioning is really a different type of 3D where you’re adding blocks. “It’s a different study involving higher density and is not the same TSV technology, However, at that level, potential cost advantages and paybacks are higher,” he said.

A comment on the floor about seeing “the same pictures as last year” sparked the question, what has changed in a year? Vardaman responded that since last march, a number of companies now offer chip-on-chip solution, which is the step before TSV. Some of the probe card companies — Formfactor, Wentworth Labs, Cascade Microtec —have been working on their probe card technologies; thermal area is showing promise; and some of the small design tool companies like R3Logic have made progress “I think you’re seeing the same pictures because people are still working on this, and aren’t ready to go public with their findings yet,” she added.

Beyne said that in Europe, 3D processes are showing up in MEMS applications and in automotive applications. He also said that a better response from EDA vendors with regard to the EDA issues is a good sign that things are coming because they don’t do anything until things are ready.

“If you’re talking about taking something from first article demonstration to high-volume production, seeing the same picture for a few years shouldn’t shock anybody." added Berry.

Beginning with the adoption of TSV for CMOS image sensors, and memory on logic in the 2008-2009 time frame, followed by backside illumination (BSI) in ’09, DRAM around 2010, and heterogeneous integration and repartitioning by 2014, Garrou asked if the panelist agree with this sequence if not these dates?

Berry agreed with the order, but also suggested that we might see some derivatives of heterogeneous integration by 2012 or 2013, with logic deconstructed on an interposer, for example. “ I wouldn’t be surprised if to see a simplified version of the heterogeneous integration show up a year earlier.” He said.

Vardaman said that other than image sensors, things have shifted out a bit due to the economic condition. “How long does it take to put a 300mm line in? Capex doesn’t look good.” She pointed out.

While agreeing with the sequence, Beyne noted that the image being used on various presentation to depict heterogenous integration “gives a completely false impression of what will happen. It will be a simpler version,” he noted, adding that it’s a question of added value. The driver from business point of view will be the advantage to “fab lite” manufacturers.
Garrou concurred, pointing out that the ability to do this in parts does have an advantage, especially from an IP perspective.

Patti said he agrees with the order of the way things will happen, and also sees it as a good time frame. “I agree flash will be behind DRAM, but phase-change memory will be before flash.” He explained that as phase-change memory is still in the design phase, it offers the opportunity to start from scratch. There’s no hurry to convert existing products to TSV, but when you’re starting with a new memory architecture, and have a problem that can be solved, it makes sense to incorporate TSV.

TSMC stepped forward with a roadmap to do TSV at 50µm pitch – willing to implement in 2011. Will TSMC hold to this roadmap or push out the iTSV production capability?

The consensus among the panel — TSMC will likely push it out. “There aren’t enough customer to justify it, so I think it will push out." noted Patti. “I’ve good reason to believe it’s likely to move because they’re demand driven. There would have to be strong customer demand.”

Berry noted that it’s a difficult business model for TSMC. “Its everyone’s best interest to wait." he said. “It’s always better to delay."

Do we all agree that for the most part, TSV will be a Fab/Foundry business?

While it seemed clear from the panel responses that the vias themselves will be created first in the foundry, who would take ownership of the post fab processes still remains to be seen. Barry said that it’s a question of risk mitigation. OSATS will be in good position to support middle end technologies.

Patti said that wherever it is, it will be important that it’s one entity that’s doing all the post-fab processes in one spot: backside grinding, surface treatment, RDL , microbump, die stacking, assembly and test. He added that since foundries got burned in the bumping business, he sees the task being taken on by the OSAT providers — albeit by a short list of OSATS who can do it.

Offering a perspective from equipment manufacturers, Kim pointed out that transferring very thin, delicate wafers between locations is a concern. “I’m not sure who will be the ones to do it,” he said, “but multiple processes done on very thin wafers, should be done at one location.”

Aside from test, do we all agree that equipment sets are ready for production?

The general concensus among panelists was that yes, with a few modifications in some areas equipment is ready. “EVG is definitely ready.” said Kim.

From the floor, Ted Tessier of Flip Chip International pointed out that there’s still work to be done in the die placement area. “It’s not cost effective yet," he noted.

Design and Test: what is the hesitancy of Cadence and Mentor Graphics to addess the design tool issue, and should it be done under a consortium umbrella?

There was general agreement among the panel that a the design community doesn’t really lend itself to a consortium format. Vardaman observed that with regard to Cadence and Mentor, it is likely they are waiting for a small start-up company to develop the tools, and then they’ll acquire them.

Speaking from his position as an early adopter, Patti said that designs for memory can be done with existing tools. “We don’t like it, it’s a lot of heavy lifting, but it can be done,” he said. However, it will be a problem when it comes to heterogeneous integration. The bigger companies don’t have a compelling reason to develop them yet, Patti added, because they aren’t losing business to a competitor by not having a 3D solution. He named R3Logic and Micro Magic as two small design houses that currently have EDA tools for 3D.

Test – is this being done and kept under wraps?

Test was one of the most elusive areas, with the least amount of response among the panel and audience alike. Patti said he’s not sure how a wafer with 1.5M channels will ever be tested. He offered Tezzaron’s solution of built in self-testing and self –repair. Ultimately, he said, you’ll need to test the final package. “Tera-computing will require self test and self repair." he added.

Approaches to testing memory and logic are completely different, said Beyne. He suggested that inspection is a more viable approach, such as with metrology tools. “A lot of metrology issues can be measured to compliment the testing." In the end, the final structure will need to be tested.

All in all, some direct answers to some fairly provocative questions. As panel discussions go, I’d say this one brought some interesting information to the forefront. If anyone who attended thinks I left something out, be sure to add your comments here. – F.v.T.