Endlich Freitag! 3D Buzz

Guten Tag! It’s Friday already? I’m not sure where that week went, but I managed to gather some interesting 3D tidbits throughout the course of it. Let’s begin with Sally Adee’s 3D coverage of IEEE’s International Solid-State Circuits Conference that took place in San Francisco this week.

It seems the big news was progress in 3D integration using TSV for all types of memory; right on schedule with Yole Développment’s predictions of TSV chip stacking for DRAM beginning in 2009 and ramping to high-growth in the 2010-2013 time-frame. Toshiba reportedly won the prize for having the first available product with its 3D stacked image sensor. Additionally, Infineon reported success in developing their second-generation wireless pressure sensor interconnected with TSVs on two levels of the 4-layer chip stack: the MEMS sensor and the transceiver.

I was excited to see the announcement of Tessera’s licensing of it µPILR technology to Kinsus, because I’ve been following the progress of the technology since I first saw Vern Solberg’s presentation at IMAPS in San Diego in 2006. The process calls for stacking logic, memory, flash and DRAM with low-profile, pin-shaped contacts, replacing traditional interconnects such as solder balls on semiconductor packages The plan is for Kinsus, a Korean-based package substrate manufacturer to make and sell substrates base on µPILR technology. It's always cool to see the baby bird find its wings and take off.

There was also some buzz about 3D chip stacking equipment in development. From the Netherlands and Austria, came TNO’s announcement of collaboration with Besi/Datacon to develop a production-level die bonder for 3D chips stacking for TSV manufacturing based on Datacon’s successful 8800 flip chip bonder. The targets chip-to-wafer processes with the intention of developing a machine that starts out with processed wafers without vias and finishes with complete die stacks.

Not far away in Switzerland, Kulicke & Soffa/Alphasem is getting ready for the SEMICON China launch of its new high-production die bonder for 3D chip stacking. According to Richard Boulanger of K & S/Alphasem, the company’s tool will focus on high-performance stacked die applications first but will extend in other markets later.

There’s a lot more to both these stories, and I still have lots of questions that need to be answered, so look forward to more on these developments next week since the work day is already over in Europe. Schonen Wochenende!

Other 3Ds: HIDING DIES/HERMES projects update

Tuesday’s post, which referenced the Fraunhofer IZM’s work in embedded die technologies to achieve 3D packages, reminded me that I hadn't seen much in the news about it since the announcement of HERMES partnership with Flip Chip International last July, following the launch of FCI’s Embeddable Die Customization (EDC) technology. HERMES is the follow-on project to HIDING DIES, and is focused on the industrialization of embedded die processes. The goal was for FCI’s technology to provide part of the infrastructure that would help take HIDING DIES from the development stage to high-volume production. With HERMES’ one-year anniversary coming up in May, I decided it was more than time to weigh in on the progress.


Here’s what I learned. In October, Lars Boettcher, Dionysios Manessis, Andreas Ostmann Stefan Karaszkiewicz and Herbert Reichl, members of the HERMES project research team, received the 2008 Outstanding Paper Award at the 3rd IMPACT and 10th EMAP Joint Conference in Taipei, Taiwan for “Embedding of Chips for System in Package Realization – Technology and Applications”.

In addition to offering an overview of the generic chip-in-polymer technology, the paper discusses development of the technology further to realize 3D SiPs, and new challenges that must now be addresses as a result. According to the paper, a related goal of the HERMES project is to unearth and address these challenges, and once they are validated at prototype level, to develop a business model that would merge PCB and component manufacturing lines to produce these high-density devices at low-cost.

It appears that the team is ready to tell the next chapter in the story at IMAPS Device Packaging Symposium, on Thursday, March 12, from 9-9:30am. If you’re interested in following this progress, be sure put “Chip Embedding Technology – New Technological Challenges for a Reliable System-in-Package Realization" on your technical agenda. Somebody save me a seat up front. - F.v.T.

Other 3Ds: The many uses for LCP

Last fall before SEMICON Europa, Andreas Ostmann, manager of the embedding and substrate technologies group, Fraunhofer IZM, spent some time with me explaining what he decribed as 3 distinct levels of 3D packaging. The first was die stacking through TSV. The second was what he termed a reconfigured wafer of molded single chips, citing as examples Freescale’s redistribution chip package (RCP), and the embedded wafer-level ball grid array, (eWLB) a collaborative effort of STATS ChipPAC, STMicrolectronics and Infineon. The third involves embedding chips into organic materials using PCB technologies. Ostmann's own work at the Fraunhofer IZM, chip in polymer, via the Hiding Dies and Hermes programs, falls in this category.

In this third category, I’ve been following the work of a research group at Georgia Tech, who is developing an embedded 3D technology using liquid crystal polymer (LCP) as a base material. Due to its dielectric properties, flexibility, and near-hermetic nature, LCP can be used as a substrate, dielectric and sealant for 3D construction, making an all-LCP package a viable option. Swapan Bhattacharya and John Papapolymerou, of Georgia Tech’s School of Electrical and Computer Engineering have been leading this research, and have contributed a series of articles to Advanced Packaging magazine, outlining their work. Four of six parts have been published:

3D LCP Package Technologies Parts 1-4:
Part 1: Embedded Actives
Part 2: Laminated Thin Film Resistors on LCP
Part 3: Power Dividers on LCP
Part 4: Electroless Plated Thin-film Resistors on Organic Substrates

I'm looking forward to Parts 5 and 6, to round out the series. - F.v.T.

The Other 3D Packaging Technologies

While TSV developments continue to attract media attention as the rock star technology of 3D integration, it’s important to remember that it’s not the only game in town. As a member of said media, I must admit that it’s easy to get caught up in all TSV all the time, because it’s been exciting to follow, and there are a lot of elements that need to fall into place for market adoption. Therefore, it’s an easy target. But what about other 3D technologies that are making progress? Any journalist (or blogger) worth his or her salt knows that the best story ideas require a little digging, so here goes. This week I’ll focus on bringing readers up to date on some of these.

Vertical Circuits’ Vertical Interconnect Pillar Technology
Abbreviated to the acronym, VIP (clever, don’t you think?), this technology was developed as an alternative to both wire bond and TSV, overcoming scaling limitations of the former (up to 100 die have reportedly been proven) and design and cost limitations of the latter. VIP is actually the final step in a series of process steps that begins with standard die in wafer form. Die pads are re-routed to the periphery, and the die goes through an insulation process. The wafer is then thinned and die are singulated. Next the die are stacked and laminated together with an adhesive. Finally, conductors are jet dispensed on the edge of the die stack using Asymtek’s high speed, high accuracy jetting technology. The process involves existing equipment, and can be integrated into any existing back-end assembly line. Target applications include memory modules, embedded memory, and system-in-package.

This company and its technology made recent headlines with the announcement of its strategic partnership with DISCO, known for its high volume manufacturing (HVM) backgrind and dicing tools. As VCI’s process relies on wafer thinning and dicing techniques, the partnership allows them to offer an established toolset to the IDMs and packaging companies that license its technology.

Look for presentations from VCI at several upcoming industry events including IMAPS Device Packaging Symposium, ISTC/CSTIC 2009 (part of SEMICON China), 2009 MRS Spring Meeting, and ECTC 2009. – F.v.T.

TGIF 3D Buzz #2

A German friend of mine suggested I might want to keep my European readers in mind when I use typically American catch-phrases in my blog, such as the title of my Friday blog posts. So just in case anyone reading was wondering what TGIF stands for, it’s Thank God Its Friday. This gives me an idea. Lets make this international. Submit a similar sentiment in your native language, and I'll use them as subsequent Friday blog titles. It's Friday, afterall, we're allowed to have a little fun.

So — on to topics pertinent to 3D….a headline in today’s Semiconductor Packaging News, which linked to a story in Cybermedia Online India caught my eye – "Semiconductor Industry Recession then Boom!" As you know, I’ve been avoiding any of the doom and gloom, but the "boom" in the title made me click on the link. Could it be good news? YES! Finally. Thank you, Bill McLean. You’re a man after my own heart. While 2009 overall may still see negative growth, McLean recommends looking at it quarter by quarter. Recessions are usually followed by periods of strong growth, and McLean predicts that to begin by the 3rd quarter. That’s more like it. I’m going to shake your hand next time I see you.

Lee Smith of Amkor and I chatted a bit yesterday about a market rebound and where 3D technologies fit into this. He said that even when there’s a major market crash, development is still ongoing. Fueling productization requires compelling innovations. Even through a down cycle, Amkor introduced three packaging innovations. Two of them - FusionQuad and FC^mBGA – were developed to provide next-generation solutions using existing infrastructure. The third, which will be launched soon in the 3D packaging space, is TMVPoP. This package-on-package design uses lasers to create interconnects between the top and bottom packages allowing memory/logic interface with finer pitches, higher density, and a thinner bottom package to accommodate more configurations.

Other interesting tidbits this week….
Henkel Corp. announced the appointment of Luc Godefroid as the company’s Global Sales Director for its Semiconductor Group. Since the company’s acquisition of National Starch, Godefroid has been leading the integration process as head of project management. With that task well underway, the company says it has decided to leverage Godefroid’s advanced materials knowledge and management skills by transitioning him to lead the semiconductor group.

SUSS MicroTec announced that Frank Averdung is ready to take the helm four months ahead of schedule. Franz Richter, Ph.D., chairman of the supervisory board, says he’s pleased with that Averdung is available early, because his industry and marketing experience is “invaluable to the strategic advancement of the Company. to the strategic advancement of the Company.”

And lastly, Ultratech received the Zurich North America Commercial and Wells Fargo Insurance Services' award, which acknowledges companies whose corporate culture makes safety a "value system." The company’s track record for employee health and safety certainly establishes them as an industry benchmark.

That pretty much wraps up the week. Enjoy the weekend. I’m sure there will be much more to talk about next week in the wonderful world of 3D IC Packaging. – F.v.T

GBC 2009 - A 3D Packaging Junkie’s Dream

When I opened Lee Smith’s email yesterday to find the updated agenda for Spring 2009 IMAPS Global Business Council, I thought maybe I’d died and gone to 3D heaven. Called “Supply Chain Development for 3D Packaging”, the agenda for this one-day event preceding the Device Packaging Symposium is jam-packed with keynote-level speakers whose presentations span the 3D spectrum, giving air time to much more than the latest in TSV, although it certainly gets its due. Committee co-chairs, Lee Smith, VP of business development at Amkor, and Jie Xue, Ph.D. director of technology and quality at Cisco Systems, Inc. have done such a stellar job of putting together a content-rich program that I predict standing-room-only.

"I am very pleased with the overwhelming support we received from industry experts to speak at this event,” says Smith. “I've been involved with 3D packaging from folded flex assemblies to TSV interconnects over the past 28 years and believe this conference is a must-attend for anyone who is looking to develop, use or supply 3D IC, TSV or 3D packaging technologies.” He added that the GBC forum’s high level of speakers and attendees fosters open communication and is unique because rather than discussing technologies or products, the focus is placed on the business and logistics issues associated with developing a capable supply chain, which is critical to both users and suppliers.

This year Jan Vardaman, president, TechSearch International sets the tone with her keynote, “Market Demand, Applications, and Requirements for 3D Packaging and 3D ICs”. The morning session focuses on supply chain collaboration from R&D to commercialization of 3D ICs with TSVs beginning with "The Role of Consortia", featuring presentations by Rosalia Beica of EMC3D, and Eric Beyne of IMEC. Next, executives from several IC suppliers offer their perspectives. Among them, Bob Patti, of Tezzaron offers insight as an early supplier of 3D IC products, talking about obstacles his company faced due to lack of supply chain infrastructure.

During lunch, Bill McLean of IC Insights will offer a keynote on an upbeat topic, “Poised for Quick Rebound”. Hopefully this will help boost attendee optimism about the economic climate, or at least get us through desert without causing a room full of indigestion.

The afternoon is divided into two sessions, “3D Packaging, TSV, Roadmap, and Supply Chain/Technology Development” and “Multi-sources of Supply and Lessons Learned from 3D Packaging-based Products”. Here’s where other 3D flavors share the spotlight with TSV. Bill Bottoms of Nanonexus will talk about system-in-package (SiP) integration for 3D, Bob Lanzone of Amkor will unveil the company’s next-generation package-on-package (PoP) built on its proprietary through mold via (TMV) technology platform, and Marc Robinson, CTO of Vertical Circuits, will no doubt at least touch on the company’s jetted silver-filled polymer interconnect technology for chip stacking in his presentation, “Rolling Out a New Packaging Technology; Maximizing Supply Chain Opportunities.”

For maximum value, Smith recommends that technologists and business leaders consider coordinating their companies participation in the GBC and the two and a half days of strong 3D technical papers and exhibits that follow at the IMAPS Device Packaging Conference. “Within Amkor, we see the GBC and DPC as our top conference for 2009 participation; due to the quality of the topics, speakers, attendees," he says. "and of course our Arizona weather in March is a huge draw."

Let’s see, all the 3D I could possibly want to know about; a 3-day exchange of ice and snow for warm sunshine… I’ve heard enough. Come March 8-11, you know where to find me and my laptop. Hope to see you all there. – F.v.T

ALLVIA – A TSV Success Story

Is ALLVIA ahead of the pack? While the rest of us wonder when through silicon via (TSV) will be ready for market adoption, a small Sunnyvale-based company, ALLVIA, has been chugging right along for the past five years, manufacturing TSVs for a variety of applications like advanced vertical interconnect, silicon interposers for system-in-package, and MEMS sensors. For the past 3 years, they’ve even been generating revenue through prototype services and volume production runs at its fab facility.

Just today, AllVIA announced it has received the third round of funding to allow expansion of the facility and build more capacity. Here. In the US. During a recession. With a technology that’s still, for the most part, trying to break out of the gate. What could be better news than that?

I first met Sergey Savastiouk, CEO of ALLVIA, at IMAPS 2008 and he talked to me about the company’s history. He said he first licensed the technology and developed equipment for TSV processes in 1996, but it drew no interest. So he set about building a foundry to change all that. He even coined the name — through silicon via.

In 2005, ALLVIA began working with customers — MEMS sensors and packaging people — to integrate vias into products and generate missing data. Since then, Savastiouk says the have been working to develop reliability data, costing and manufacturability parameters, which he says are the keys to transport TSVs from niche to volume production.

“As a technology TSVs are going through a similar life cycle as flip chips,” commented Savastiouk. “Flip chips were first developed in the 1960s by IBM. But it took decades to develop the feasibility, reliability, cost effectiveness and manufacturability to get them into volume production. TSV has passed the feasibility phase, but reliability and manufacturability figures, and most importantly, those applications that are willing to pay for the technology, are still being determined.” Savoustiak also said the timeline could be accelerated if a company such as Intel were to lead the charge.

This latest injection of cash – reportedly $5M – brings the company’s investment total to $25M. Looks like ALLVIA is drawing interest now. – F.v.T.