Jisso International Council 2009: Defining 3D

Last week, I heard from the North American delegation of the Jisso International Council (JIC), reporting on the recently concluded annual meeting at the Minatec facilities in Grenoble France, which this year was focused on 3D terminology. Collectively, they contributed the following guest post:

The Jisso International Council (JIC) successfully completed its 10th annual meeting at the facilities of Minatec in Grenoble, France, at which the third dimension was a key topic. JIC’s interest in 3D is predicated on their ongoing efforts to harmonize standardization and industry terminology for electronic interconnections. 3D interconnections are blurring the once well-defined and bright lines that separated the various hierarchical elements of the electronics universe. As a result, the council is now looking for ways to help the broader industry communicate more effectively as these nascent technologies begin to take hold and grow.

There were several excellent and informative presentations made by council members in an effort to help identify and resolve some of the many challenges that accompany the development and growth of this new area of high interest to the electronics design and manufacturing community. In the first part of the JIC’s 3D session, Eric Beyne, IMEC (Belgium), Nicolas Sillon, CEA- Léti (France) and Juergen Wolf, Fraunhofer Institute (Germany) provided a comprehensive review of the economical considerations of the various TSV technologies that are increasingly popular.

3D technology, it was concluded, is essentially a collection of stacked chip versions using both “vias-first” and “vias-last” production methods. Related technologies not only allow for the stacking or layering of interconnect routing layers, as has long been the design tradition, but now also allow the stacking of actual active component layers to provide a “More than Moore” total integration solution. This is perhaps the most distinctive feature of 3D integration, as it allows for the realization of electronic systems with a much higher packaging efficiency, measured both in terms of density per unit area and per unit volume.

The second session reviewed TSV-3D applications and production scenarios with presentations by Hirofumi Nakajima, NEC (Japan), Claudius Feger, IBM (USA), Bernd Roemer, IFX (Germany), Caroline Beelen-Hendrikx NXP (Belgium) and Jacques Ferrara, ST Micro (France). Their presentations indicated that application drivers for 3D technologies are numerous and diverse. Among the top drivers were reduced size and form factor, which are obvious ones, but there are others drivers as well.

For example, device bandwidth and clock frequency are basically “flat-lining” in the world of 2D interconnections, and there is a need for more heterogeneous integration including RF, analog, logic, memory and sensors. Another driver is power reduction in an increasingly power hungry world. Other advantages include modularity and the potential of IP re-use to lower time-to-market and cost.

In summary, 3D technology is definitely on the rise both figuratively and literally, but there are many hurdles still to clear and much understanding still required. The technology resides largely in the domain of research but is rapidly moving to production. It seems clearly to be headed to a bright future, but its success will be gated by the quality of the communications that are employed to carry forward and codify the lessons learned.

Just as I'd hoped, it seems as though Françoise in 3D is becoming more than just a blog, but also a forum for the 3D community to contribute information. Keep it coming! -- F.v.T

Walker confirms; SATS Industry is healthy

Yesterday's post resulted in an email from Jim Walker, Research VP, Semiconductor Manufacturing, Gartner Dataquest. I've known Jim for several years, as he served on Advanced Packaging magazine's advisory board, and have often consulted with him on market research for the Semiconductor Assembly and Test Services (SATS) sector. I thought his comments should be shared with my whole readership as more than just a comment to the original post. So with his permission, I've decided to post his email here, in its entirety:

Françoise –

Thanks for writing your blog on the SATS market today. It appears that someone in the press was taking 2 separate recent reports we wrote on the SATS market and combined them into one, resulting in confusion for the readers. One report on the SATS market share for 2008 (which you referenced) dealt with revenue numbers. The other report, by David Christensen, our factory database analyst, discussed manufacturing facilities and the square footage of factory space that has and will be changing over the next year regarding IDM and the SATS companies. I agree with your assessment that the SATS industry is healthy and not in 'dire' straights.

I have received a lot of emails concerning the articles and wondering what was going on with the industry.

Regards,

Jim Walker

So there you have it, straight from the source. Thanks for clarifying that, Jim. -- F.v.T

Is SATS revenue declining or relocating?

What’s that you say? The SATS sector is set for further declines? Really? Or is that yet another negative perspective being expressed by the trade press? Ok, one publication’s headline reporting Gartner’s latest findings grabbed my attention, while I experienced that “oh no here we go again” feeling in the pit of my stomach. Further reading on other industry sites unearthed a more balanced picture. Yes – numbers are down due to the global economy. Nothing earth shattering there. But the solid numbers reported past revenue from 2008 backwards, and anything going forward is purely speculative.

Let’s talk about what’s really happening. Although the SATS sector reported losses last year, they still outpaced the overall semiconductor industry. In fact, several of the OSATS providers – STATS ChipPAC, Unisem, and Powertech all reported growth over 2007. The expected 40% drop in back-end semiconductor manufacturing capacity is reportedly expected at IDMS not the OSATS providers. That number has more to do with IDMS and OEMS adopting an outsource model and shifting the work to packaging houses. As a result, Gartner predicts a 60% capacity increase for the OSATS in the same time frame. In fact, ASE recently reported being awarded a sizeable contract by Intel. One big enough, in fact, that it is likely to boost ASE’s revenues past the expected level. The contract is reportedly due to Intel’s closing of in-house packaging and test facilities.

According to an article I read in Taiwan Economic News, other IDMS such as NXP Semiconductor, Renesas, and Toshiba are expected to follow suit; and other OSATS will benefit. So rather than an overall loss in revenue wouldn’t this be more appropriately termed a shift in revenue? And don’t all parties ultimately benefit as resources are conserved in one place as they are expanded in others? I think they call this restructuring, and at the end of the day, the industry as a whole might just benefit.

So how does this relate to 3D technologies? Clearly, OSATS play an integral part in market adoption of 3D IC integration technologies. I suggest that volume production of 3D WLP and 3D IC stacking using TSVs could be the missing variable to tip the scales in the favor of OSATS who invest in those production capabilities. When numbers are reported next year, will the companies who took on the challenge be the ones reporting growth? That’s what I want to know. – F.v.T.

Can cost-sharing accelerate 3D IC commercialization?

I’ve been talking a lot about the collaborative efforts in the form of open and closed consortia and joint development agreements that seem to be carrying 3D IC integration forward to market adoption. Another approach is a multi-project wafer program, in which participants cost-share to build multiple device prototypes on a single wafer. The intention is to bring the resulting prototypes to commercialization more quickly and at a lower cost to each member than if they were developed individually.

One such program is Tezzaron Semiconductor’s multi-project wafer program, first reported a few months back on Phil Garrou’s 3D blog, Perspectives from the Leading Edge. According to Garrou’s post, the project would allow up to 10 participants to buy a share of wafer real estate for the purpose of developing prototype 3D IC logic devices. The intention was for each participant to design its own 3D logic device, which would be built in Tezzaron’s proprietary FaStack process. Each logic device would then be integrated with a Tezzaron 3D DRAM to create a hybrid memory/logic 3D-IC. Hmm, I thought, cool approach. I need to find out more.

Unfortunately, the project went dark,(it was initially sponsored by DARPA, and mum’s the word when government agencies are involved.) However, the embargo has lifted, and last week I had a lengthy chat with Gretchen Patti, of Tezzaron Semiconductor. While she couldn’t reveal details of specific devices being tested in 3D by participants, she did say they primarily fell into one of two categories; processors and sensors. For the non-techies among us (like me), Patti offered a simple description of the process.

Figure 1 illustrates how two levels of logic are being built on one wafer. Suppose that the two red squares belong to a participant prototyping a processor, the two yellow squares belong to a participant prototyping a sensor technology, etc. The processor is designed with two layers of circuitry. One layer is built in the red square on Side 1, the other on Side 2. Similarly, the sensor is designed with two layers of circuitry that are built in the two yellow squares. Now we build a whole bunch of identical wafers. Each wafer is stacked face-to-face on an identical wafer. In this way, the sensor dies line up, and the processors line up. When the wafers are bonded, the sensor’s two layers of circuitry become a single circuit, and so do the processor layers. The final project wafer consists of different logic devices, each designed by a different participant.

Next, logic devices are then stacked on a Tezzaron 3D DRAM wafer, which was also created as a wafer-to-wafer stack using tungsten-filled TSV interconnects. The final output is various logic-on-memory devices, assembled in a die-to-wafer process using TSV interconnects (Figure 2). One of the benefits of multiple projects being designed using the same memory wafer is that the logic is then designed to interface with a standard memory, so that although the memory wafer is not customized to each device, it attaches as if it was.

According to Patti, the project has taken on a life of its own, and has grown beyond the original intention to include 19 participants from both the public and private sector, including several universities (U. of Pittsburgh, U. of Michigan, and Johns Hopkins, to name a few.)

“We couldn’t believe the response,” she said. “We didn’t even publicize it.” They ended up with 30 applicants, more than twice as many as they expected. There’s no doubt about it, it’s an attractive alternative for companies who can’t swing their own processing costs, but want to test their product to see if it works in 3D. “People are ready,” notes Patti. I’ll say. Look for more on this as I talk to some of the university participants about specific projects. – F.v.T.

3D innovation: prevention or cure?

In his editorial yesterday, Steve DeCollibus, managing editor of Semiconductor Packaging News, offered some food for thought about the concept of the semiconductor industry innovating its way out of this downturn. To illustrate his point, he tracks the evolution of the integrated circuit itself – a technical innovation that took 80 years to complete.The point he makes is this: true innovation takes time, dedication, collaboration, and full participation of everyone from academia and R&D, across the entire supply chain. It’s not something that can be done, as he puts it “on demand.” I couldn’t agree more.

Innovation shouldn’t be seen as the antidote, or cure to the current economic pandemic. Rather, ongoing treatment seems to be much a much more potent measure against the disease. For example, 3D integration technologies have been the innovation flavor-of-the-month since long before the current economic disaster hit. Is it by pure coincidence that those companies who continued to push forward and invest in these technologies are the ones who were more resistant to the downturn virus? I’m talking about start-up companies like Alchimer, Replisaurus and Imbera, who managed to raise venture capital to develop their technologies; and established equipment manufacturers like SUSS MicroTec, Surface Technology Systems, and EV Group, who have all recently reported installs in both research and production settings. According to Steve Dwyer, director of sales, North America, EVG, in the past 3 weeks, EVG has received 6 tool orders for TSV processes in North America alone, 4 of which are headed for production lines, while the other two will go to research settings.

Although it may seem that the “Pollyannas” of the industry (myself included) have been dishing out the “innovate out of the downturn” mantra as a way to bolster morale, it’s not without basis. However, perhaps a more accurate explanation is that during a downturn, there is less time spent manufacturing and shipping product, and more time to focus on innovation. The companies who took advantage of that time seemed to be hit less badly by the downturn, and those who were already innovating and continued on that path were the most resistant to the effects of the downturn. After all as, Benjamin Franklin once said, an ounce of prevention is worth a pound of cure. – F.v.T

Semi Standards – a 3D conundrum?

I got into an interesting conversation recently with Steve Dwyer, of EV Group, about the puzzling situation 3D IC integration is posing with regard to existing Semi Standards, and those yet to be established as 3D IC integration processes are developed.

Take, for example, the standard for wafer handling. Dwyer explained that the current standard calls for a process wafer to be returned to the same slot in the FOUP where it came from. But with temporary bonding for thin wafer handling, the input comes from two separate FOUPs, and the output is the two wafers bonded together, so one FOUP winds up with an empty slot, thereby breaking the standard for handling wafers. Clearly, the standard was set based on single wafer processes, and didn’t consider future possibilities of multiple wafers being combined into a single processed wafer.

Additionally, when it comes to establishing standards for 3D IC integration processes, all the different processes being developed — via-first, via-early, and via last; front side approaches vs. back-side approaches; wafer-to-wafer, chip-to-wafer and chip-to-substrate — will need to be considered.

So what’s the hurry? Is the establishment of standards for 3D IC integration critical for market adoption to take place? Would it be better to hold off until the processes shake out and we see what sticks? Consider also that if multiple approaches are adopted, then standards will need to be set to accommodate different options. “Until the industry works out what it wants to do, we need the flexibility,” notes Dwyer.

I posed this question to Sitaram Arkalgud of SEMATECH’s 3D interconnect program, and Rich Brilla, of the College of Nanoscale Science and Engineering (CNSE) at the University at Albany. Brilla noted that in addition to standards focused on equipment and processes, design ground rules are also needed. For example, knowing where alignment marks should be for wafer to wafer and chip to wafer processes is critical. Part of the work being done by SEMATECH at CSNE will help to establish these standards.

“It takes ages for standards to come together. It’s a voyage of discovery,” notes Arkalgud, adding that this work-in-progress approach to standards is still better than having nothing at all. “3D can revolutionize the industry, but needs standards in order to make it happen, otherwise it will delay the adoption of technology,” he said; a sweeping statement perhaps, but his point is well taken. Without standards to bring the technology to high volume, it runs the risk of just being a niche market. – F.v.T.

Another step forward for EDA Tools

I have to admit, I’ve always had difficulty trying to wrap my head around software, especially design tools. So I’ve come to have a deep respect for those individuals charged with the task of designing the design tools themselves. Not only do they need to be able to visualize the end result, they have to work backwards to anticipate the steps required to get there, and then figure out a way to archive that knowledge for later use. In essence, before a design tool can be designed, the methodology of the steps to achieve this must be established. Then, EDA tool designers create a tool based on these established methodologies to be able to automate the design processes for manufacturing.

Current 2D tools have no notion of a 3D hierarchy and thus no way to build IP libraries for 3D. To design 3D ICs, designers had to resort to tricking 2D tools by renaming design layers or creating multiple copies of standard cell libraries. This “design-by-hand” works fine for 2.5D structures like CMOS image sensors and homogenous 3D DRAM memory stacks, but as Lisa McIlrath, of R³Logic, pointed out during the panel discussion at DATE 2009, logic/memory stacks and true heterogeneous integration will need fully functioning 3D design tools.

Understanding the ramifications of this is what makes R³Logic's latest achievement of that much more noteworthy. The company was recently awarded a patent for “methods and systems for computer aided design of 3D integrated circuits”. According to a company statement, the patented invention comprises both the method of defining a 3D technology file that can incorporate one or more 2D wafer technologies corresponding to different tiers in a 3D stack, and that of defining a 3D hierarchical structure for functional blocks within a 3D system. Managing multiple design libraries while properly handling IP blocks that reside on more than one tier is crucial to 3D system design, notes R3Logic, whether at the circuit layout or at the system architecture level.

Achieving this milestone brings th 3D design pioneer another step closer to proving the industry with the tools they’re seeking. I offer my congratulations and look forward to hearing more about it. – F.v.T