SUSS MicroTec: A 3D Approach

It’s been a few years since I toured the US headquarters of SUSS MicroTec in Waterbury VT, so when general manager, Wilfried Bair invited me out to see their latest toolset developed with 3D integration processes in mind, and get the scoop on the company’s new temporary bonding and debonding system, I jumped at the chance.

Wafer-level packaging, MEMS, and LED have long been the foci of SUSS MicroTec, but as 3D integration and packaging processes emerge as pivotal to the semiconductor industry, SUSS MicroTec has adjusted its strategy. Rather than adapting existing tool sets to also handle 3D integration processes, 3D now tops the priority list, and all 300 mm equipment in development has been optimized with 3D processes in mind first, which in turn benefits the existing markets with higher performing tools. Wilfried Bair, general manager of SUSS MicroTec’s bonder division, and V.P. of business development worldwide, describes this win-win situation: “3D is driving innovation,” he says, and every other market we serve benefits.”

In his book, Handbook of 3D Integration: Technology and Applications of 3D Integrated Circuits, Dr. Phil Garrou, identifies 9 potential process variations for 3D IC stacking involving via formation, (vias first, middle, or last); thinning (on temp. carrier or 3D stack); temporary and/or permanent bonding (face to face or face to back bonding). Regardless of which variations shake out as standard, SUSS MicroTec has tools to cover it from patterning for TSVs (mask aligners and coaters), to bonding and stacking for either wafer-to-wafer die-to-wafer stacking (permanent bonding) as well as temporary bonding and debonding.

By far the most exciting piece of news Bair shared, (and one I had been waiting in anticipation for quite a while) involved the Bonder Division’s flagship platform, the XBC300, which offers a complete line of process modules for permanent and temporary wafer bonding. Of specific interest is the temporary bonding and debonding system that supports several different material processes that exist in the market.

Until the recently announced agreement with 3M, SUSS MicroTec has focused on the work with T-MAT, a German start-up company. To demonstrate the elegant simplicity of the T-MAT process, Bair first walked me through three comparable processes that can be performed on the XBC300, whose modules have been configured for temporary bonding (SC300 - Spin Coat for process integration and simplification; PL300T - Plasma to form release layer; LF300 - Low Force bond).

In Brewer Science's Thermoslide process, the device wafer is flipped face down and temporarily bonded to a carrier wafer that has been first coated with an adhesive by spin-coating and baking. The device wafer is aligned and bonded and backside processing occurs. During the debond process, an electrostatic chuck is secured to the backside of the wafer (now on top) and by applying heat, is slid off the carrier wafer. It is then flipped while still attached to the chuck, cleaned, and then either flipped again and attached to a dicing frame for die-to-wafer stacking; or aligned and permanently bonded for wafer-to-wafer stacking. Bair notes that this process is not easy to do, requires multiple process steps, and is therefore expensive. It also has issues with delamination during the debond step on 300mm wafers.

The 3M process, by comparison, requires only one carrier transfer in the temporary bonding step. In this scenario, both the device wafer and the glass carrier are spin coated with a material; adhesive on the wafer, and a release layer on the carrier. The wafer is then flipped and bonded to the carrier by means of a UV curing step. After backside processing, the debonding processes is simple: the thinned device wafer is flipped and attached to the dicing frame, the release layer is activated by means of a laser to remove the carrier wafer easily, and then the adhesive is peeled away from the device wafer, which is subsequently cleaned and ready for stacking. Bair says this is an easier process, and although there is an additional bonding step, it’s fast and clean and can be done at room temperature.

The T-MAT (shown below) process further simplifies debonding by spincoating a precursor (elastomer) on both the device wafer and carrier wafer in the bonding process, and then using plasma to form the release layer. The device wafer is flipped and temporarily bonded to the carrier wafer. The debond process is simple. Wafers destined for W2W stacking are precision-aligned and permanently bonded. Those destined for D2W stacking are attached to a dicing frame. In either case, debonding is a cold process, and requires only a small gap to be made between the carrier and device wafer so it can be lifted off.



Bair’s philosophy – and therefore the basis of his approach for business development at SUSS MicroTec is simple: Provide the whole infrastructure. Build equipment that is standardized and flexible. When a new process pops up, make sure it can be accommodated. “Customers want bonded wafers, at lowest cost, with highest yield,” says Bair “How we do that is our problem.” Enough said. -- F.v.T.

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Countdown to SEMICON West 2009

With only 2.5 weeks to go (you're all saying, really? it's that close?) until SEMICON West, I can see the activity building around this year's event. I've already talked about the increased focus on 3D this year. One thing I didn't mention yet are the various awards programs that are happening....or not.

Semi's own Best of the West Awards, launched last year to promote innovation and recognize important product and technology developments in the microelectronics supply chain, is back again for it's second year. The finalists were announced this week, and according to a press release, were selected "based on their financial impact on the industry, engineering or scientific achievement, and/or societal impact." On that list for the second time in two years is Alchimer, this time for it's AquiVia wet depostion technology. Last year, the company's egViaCoat electrografting process for copper seed made the list.

Absent from this year's line-up are both the Attendee's Choice Awards and the Advanced Packaging Awards. Instead, this year Solid State Technology and Advanced Packaging will honor those who have made it through this economic downturn through efforts to "compete, innovate and achieve" by bestowing the Semiconductor Survivor Awards. If you haven't already entered, you have until June 29.

One thing's for certain, people certainly are tapping into ingenuity this year to make the most out of SEMICON West on a tight budget. I think this really says something for the overall existance of the event. I mean, if it wasn't such an icon of the industry, companies would just pull out of it all together, wouldn't they? Maybe SEMI should get an honorary Survivor Award just for that. -- F.v.T.

3D companies address critical areas

It’s only Tuesday, and already, it’s been a productive week for 3D news.

Yesterday, SUSS and 3M announced an agreement in which SUSS becomes an authorized equipment supplier for 3M’s temporary bond and debond process. As such, SUSS’s 300mm wafer bonders will be configured to support 3M’s process and materials. This ties in to SUSS’s 3D strategy, which according to Wilfried Bair, general manager, Wafer Bonder Division, SUSS MicroTec, is to provide “a flexible, modular platform” configurable to customer needs. He recently explained to me that how you debond depends on the materials you bond with. Carrier wafer processes have been used in manufacturing high power devices for years, but the requirements around 3D are different, when you consider that instead of 200mm wafers, you’re potentially dealing with 300mm wafers thinned to 50µm. The fewer the steps, and lower the temperature, the better. So the advantages to the 3M process is that there’s only one carrier wafer step involved, it’s fast, clean, and can be done at room temperature.

Today, Alchimer SA, made a three-fold announcement, leading off with the news that it received its 3rd round of funding in the amount of $10M to expand customer-support programs and pursue new IP development. This is a significant achievement given the current economic climate. Additionally, the company formally welcomed Kathy Cook aboard as business development manager, who brings a solid background from previous positions at SUSS MicroTec, Applied Materials, Millipore, and ULVAC Technologies. (Incidentally Kathy, don’t let them call you “veteran” again in a press release. It makes you sound MUCH older than you are.) Alchimer also announced an agreement with Nagase Ltd., a Tokyo-based marketing firm, to help them meet the demand of the Japanese market.This news, coupled with last week’s announcement that the company had achieved an 80% reduction in cost-of-ownership for its egViaCoat processes indicates that this company is really on to something with this low-cost wet deposition alternative for TSV copper seed.

Lastly, DEK international stepped into the 3D arena, combining efforts with CHAD to incorporate DEK’s thin wafer system with CHAD’s wafer handler, thereby addressing traditional challenges associated with high-speed handling and processing of thinned wafers for emerging 3D packaging, wafer coating and ball placement processes. The companies plan to demonstrate their capabilities during SEMICON West. I look forward to learning more about this at the show.

Individually, these announcements have nothing to do with one another, but collectively, they can be used to illustrate how the industry is addressing some of the remaining critical areas of 3D integration with TSV interconnects. Insulator barrier/ seed, and wafer bonding; — particularly temporary bonding and debonding — and thin wafer handling have been pointed out as areas still needing cost-effective solutions. Looks like we’re making progress. – F.v.T.

3D processes and approaches: stepping stones to market adoption

I recently had one of those moments of clarity that comes from asking different people the same questions and fitting all the varied answers together like a puzzle to come up with the big picture. In this case, the questions had to do with the various approaches being developed to achieve 3D integration using TSVs – namely, via-first, middle and last for via formation; and wafer-to-wafer (W2W) and die-to-wafer (D2W) for device stacking. One thing is for sure, there is no shortage on opinions out there surrounding these issues.

At the risk of oversimplification, I offer up the following analysis; perhaps the best way to understand how 3D integration using TSV will ultimately come together is to see it as a progression – a stepping stone approach. Even though that’s how the questions are often posed – it’s not likely to end up as an either-or situation.

D2W currently achieves better yields than W2W, but once the known-good-die issue is figured out, W2W will be a more cost-effective process because it is done in parallel. Via-middle will most likely be the TSV champion, once design and test tools are available; but until then, some predict that the first products will be built using via-last, which can be done with existing die. It’s a matter of convincing the industry as a whole (and there are still many who remain skeptical that TSV itself is the answer) that overcoming current limitations for W2W and via-middle is a worthy investment.

Regardless of how things shake out, the equipment and materials manufacturers are covering their bases by making sure their tools and chemistries adapt or exist for all possible variations. Because no matter which processes are adopted for volume production, there will always be niche applications that are better suited to the processes that don’t reach volume production. – F.v.T

Are you an oldtimer or a newcomer?

It has nothing to do with age, and everything to do with whether you have the ability to embrace new and exciting things, or whether you deem them unworthy of your time.

When it comes to communication, we live in a rapidly changing world. A couple of years ago, using the Internet as a means of communication was still fairly linear. E-mail and IM were firmly established for two-way communication, but Skype was just starting to be accepted, and social networking for both personal and professional purposes was very much on fringe – used only by the savviest and most trendy adopters of technology; college students, teenagers, rock stars, and other social elite; or professionals looking to build their networks. In the past year that has changed dramatically, as people from all walks of life discover the usefulness of these methods of staying in touch, when used with respect.

I “talk” to lots of people every day – on the phone, via email, Skype, LinkedIn, facebook, in web meetings on SemiNeedle, and finally just a few days ago, on Twitter. As an industry commentator, these have become the tools of my trade. I find them incredibly efficient methods for connecting with colleagues and friends from around the world, as well as for sharing information. I don’t worry that it imposes on my time, because I know how to set an out-of-office email, and how to power down my laptop and cell phone. So I don’t really get when people, especially those in the business of gathering and sharing information, say “I don’t have time for those things.” I think what they’re really saying is, “I don’t have time to learn how they work and incorporate them into my lifestyle”.

In my opinion, if you’re in the communication business, these tools can actually help save both time and money, and are worth the time investment of becoming familiar with them. The truth of the matter is, those teenagers and college students who started using them from the beginning are joining the workforce, which means that over time, they will replace traditional methods of exchanging information. After all, most of them are so easy, even a child can use them…

So which are you, an Oldtimer or a Newcomer? -- F.v.T

3D is hot at SEMICON West

Given the building momentum around 3D integration schemes and the attention it's getting as the semiconductor bright spot, it's no surprise that at this year’s SEMICON West, there are more programs focused on 3D integration technology issues, both on and off-site, than last year. In fact, if you want to plan your itinerary around all things 3D, you can easily fill your schedule.(Trust me on this one, my dance card is overflowing.)

Whet your appetite by joining in the discussion online at the aptly-named, Brightspots 3D IC Forum. Moderated by yours truly, this roundtable discussion will address critical issues surrounding 3D integration from the front-end through the back-end. Discussion opens at 6am PT, on July 6 (looks like I'll be moderating this one in my jammies) and closes July 24. The more people who participate, the more interesting I’m sure it will be, so sign up early and visit often.

SEMI has organized several program events around 3D integration beginning with a Packaging Summit on Tuesday, July 14 from 3:30-5:30, that begs the question: When the Package is the Product, will 3D Integration be the Holy Grail? This summit will address the business side of 3D, discussing how these emerging technologies will overcome cost and time-to-market to find their way into consumer electronic applications. Additionally, Wed. July 15 from 2-4pm, the Test, Assembly and Packaging TechXPOT will feature a technical session, The 3D TSV Revolution, It’s More Than Just Stacking! with speakers addressing 3D integration technologies such as systems integration, system design, TSV processes, materials issues, thin wafer handling and chip stacking, as well as the OSAT perspective.

Then, the Thursday session from 11:00 – 1:20 looks at Survivability Through Collaboration, examining the effectiveness of collaboration between the R&D and manufacturing communities in bring 3D schemes to fruition. Additionally, one presentation (from 2:50-3:10 pm) during the test strategies session on Tuesday talks about Semiconductor Test in the Third Dimension. As test is one of the missing links in the 3D supply chain, it would be great to find some insight here.

Off-site, SUSS MicroTec has just announced they will be hosting a free workshop at the St. Regis, Wed. July 15 from 2-5pm on the topic of Thin Wafer Processing for 3D TSV Applications, in which materials and equipment manufacturers will reveal the latest innovations in thin wafer support systems & backside processing. Also on Wednesday from 1pm-6pm, SEMATECH will be hosting a 3D Metrology Workshop. Attendees should hope to gain information on how new and existing wafer metrology technologies can adapted to measure and improve 3D interconnect processes.

It’s pretty clear I’m going to have to clone myself, at least on Wednesday, to fit all this in! Hope to bump into you there. – F.v.T.

Which comes first, 3D standards or market adoption?

The more I talk to people involved in bringing 3D integration using TSV to market, the more it’s clear that the standards issue is another chicken-and-egg, cart-before-the-horse conundrum. Yes, eventually the industry will need standards, but can they really be set before the processes are established?

While some say that standards need to be in place for market adoption to occur, others say that market adoption will happen, and standards will follow suit to bring the technologies to volume production. What's important to understand here is that 'market adoption' and 'volume production' are not synonomous. The former hopefully leads to the latter, but doesn't have to. A technology can be adopted to the market, but only serve niche applications, correct? In any case, I’m told that first and foremost, there needs to be clear definitions of 3D integration schemes and roadmaps before standardization can even be considered.

Most agree that standards development for certain elements is necessary for 3D integration to reach volume production, they also note that not everything can be standardized. For example, I’ve heard several comparisons with flip chip technologies, noting that although flip chip has been used as a method of interconnect in volume production for some time; there are no standards for the process. Point taken – but then flip chip cannot be compared to the entire 3D integration scheme, but rather only to TSV as a comparable method of interconnect. TSVs exist in many forms, as we discussed at length last week. But it’s only one element. Therefore, it’s not the processes themselves that will be standardized; only the interfaces and interface dimensions, for example the interface of memory to logic in a 3D IC configuration. Additionally, design rules will be needed to address the gaps between front-end and back-end players.

Speculation as to who will set the standards varies from industry organizations like JEDEC, Jisso, ITRS, and SEMI; to the major foundries and IDMS like TSMC, Intel, and IBM. Ultimately, the task will fall to whoever stands to benefit most by investing the necessary resources. Really, it appears that developing standards will be an evolutionary process, and is likely to occur in parallel as 3D integration moves from market adoption to volume production. – F.v.T