Are you an oldtimer or a newcomer?

It has nothing to do with age, and everything to do with whether you have the ability to embrace new and exciting things, or whether you deem them unworthy of your time.

When it comes to communication, we live in a rapidly changing world. A couple of years ago, using the Internet as a means of communication was still fairly linear. E-mail and IM were firmly established for two-way communication, but Skype was just starting to be accepted, and social networking for both personal and professional purposes was very much on fringe – used only by the savviest and most trendy adopters of technology; college students, teenagers, rock stars, and other social elite; or professionals looking to build their networks. In the past year that has changed dramatically, as people from all walks of life discover the usefulness of these methods of staying in touch, when used with respect.

I “talk” to lots of people every day – on the phone, via email, Skype, LinkedIn, facebook, in web meetings on SemiNeedle, and finally just a few days ago, on Twitter. As an industry commentator, these have become the tools of my trade. I find them incredibly efficient methods for connecting with colleagues and friends from around the world, as well as for sharing information. I don’t worry that it imposes on my time, because I know how to set an out-of-office email, and how to power down my laptop and cell phone. So I don’t really get when people, especially those in the business of gathering and sharing information, say “I don’t have time for those things.” I think what they’re really saying is, “I don’t have time to learn how they work and incorporate them into my lifestyle”.

In my opinion, if you’re in the communication business, these tools can actually help save both time and money, and are worth the time investment of becoming familiar with them. The truth of the matter is, those teenagers and college students who started using them from the beginning are joining the workforce, which means that over time, they will replace traditional methods of exchanging information. After all, most of them are so easy, even a child can use them…

So which are you, an Oldtimer or a Newcomer? -- F.v.T

3D is hot at SEMICON West

Given the building momentum around 3D integration schemes and the attention it's getting as the semiconductor bright spot, it's no surprise that at this year’s SEMICON West, there are more programs focused on 3D integration technology issues, both on and off-site, than last year. In fact, if you want to plan your itinerary around all things 3D, you can easily fill your schedule.(Trust me on this one, my dance card is overflowing.)

Whet your appetite by joining in the discussion online at the aptly-named, Brightspots 3D IC Forum. Moderated by yours truly, this roundtable discussion will address critical issues surrounding 3D integration from the front-end through the back-end. Discussion opens at 6am PT, on July 6 (looks like I'll be moderating this one in my jammies) and closes July 24. The more people who participate, the more interesting I’m sure it will be, so sign up early and visit often.

SEMI has organized several program events around 3D integration beginning with a Packaging Summit on Tuesday, July 14 from 3:30-5:30, that begs the question: When the Package is the Product, will 3D Integration be the Holy Grail? This summit will address the business side of 3D, discussing how these emerging technologies will overcome cost and time-to-market to find their way into consumer electronic applications. Additionally, Wed. July 15 from 2-4pm, the Test, Assembly and Packaging TechXPOT will feature a technical session, The 3D TSV Revolution, It’s More Than Just Stacking! with speakers addressing 3D integration technologies such as systems integration, system design, TSV processes, materials issues, thin wafer handling and chip stacking, as well as the OSAT perspective.

Then, the Thursday session from 11:00 – 1:20 looks at Survivability Through Collaboration, examining the effectiveness of collaboration between the R&D and manufacturing communities in bring 3D schemes to fruition. Additionally, one presentation (from 2:50-3:10 pm) during the test strategies session on Tuesday talks about Semiconductor Test in the Third Dimension. As test is one of the missing links in the 3D supply chain, it would be great to find some insight here.

Off-site, SUSS MicroTec has just announced they will be hosting a free workshop at the St. Regis, Wed. July 15 from 2-5pm on the topic of Thin Wafer Processing for 3D TSV Applications, in which materials and equipment manufacturers will reveal the latest innovations in thin wafer support systems & backside processing. Also on Wednesday from 1pm-6pm, SEMATECH will be hosting a 3D Metrology Workshop. Attendees should hope to gain information on how new and existing wafer metrology technologies can adapted to measure and improve 3D interconnect processes.

It’s pretty clear I’m going to have to clone myself, at least on Wednesday, to fit all this in! Hope to bump into you there. – F.v.T.

Which comes first, 3D standards or market adoption?

The more I talk to people involved in bringing 3D integration using TSV to market, the more it’s clear that the standards issue is another chicken-and-egg, cart-before-the-horse conundrum. Yes, eventually the industry will need standards, but can they really be set before the processes are established?

While some say that standards need to be in place for market adoption to occur, others say that market adoption will happen, and standards will follow suit to bring the technologies to volume production. What's important to understand here is that 'market adoption' and 'volume production' are not synonomous. The former hopefully leads to the latter, but doesn't have to. A technology can be adopted to the market, but only serve niche applications, correct? In any case, I’m told that first and foremost, there needs to be clear definitions of 3D integration schemes and roadmaps before standardization can even be considered.

Most agree that standards development for certain elements is necessary for 3D integration to reach volume production, they also note that not everything can be standardized. For example, I’ve heard several comparisons with flip chip technologies, noting that although flip chip has been used as a method of interconnect in volume production for some time; there are no standards for the process. Point taken – but then flip chip cannot be compared to the entire 3D integration scheme, but rather only to TSV as a comparable method of interconnect. TSVs exist in many forms, as we discussed at length last week. But it’s only one element. Therefore, it’s not the processes themselves that will be standardized; only the interfaces and interface dimensions, for example the interface of memory to logic in a 3D IC configuration. Additionally, design rules will be needed to address the gaps between front-end and back-end players.

Speculation as to who will set the standards varies from industry organizations like JEDEC, Jisso, ITRS, and SEMI; to the major foundries and IDMS like TSMC, Intel, and IBM. Ultimately, the task will fall to whoever stands to benefit most by investing the necessary resources. Really, it appears that developing standards will be an evolutionary process, and is likely to occur in parallel as 3D integration moves from market adoption to volume production. – F.v.T

Filled vs. conformal vias: the consensus

Dr. Zhang, I think we have reached a verdict.

Bob Patti wrote in to confirm Anonymous Caller’s statement regarding polymer-filled, copper-lined TSVs, and also provided some additional data to support his comments. I’ve taken the liberty of paraphrasing his comments here:

With the caveat that he is not a “big fan” of conformal vias, and merely providing data, Bob stated:

“Certainly filling vias with a polymer makes sense to keep material from being trapped and depending on what processing may need to follow, it may be required. A via-last interposer might be a better solution. However, Dr. Zhang's question was is it possible to metalize both sides without filling, apparently it is, shown here in this ZyCube presentation (see slides 29-30, the CIS pictured is from Oki.)

At Tezzaron, we only use filled tungsten via first (middle) processes. I don't think copper via-first is a good alternative, except for interposers. Tungsten TSVs are, at best, limited to ~20µm depth, so copper is (at least currently) the only alternative for vias needing to go more than ~20µm deep. So interposers really must use copper. The issue with filled copper at high aspect ratios and/or large diameters is the exposure to thermal cycling. An interposer will not be exposed to numerous 300-400°C temperature cycles, as a copper via-first chip would be. So interposers are far more likely to tolerate filled vias.

Most memories that I am familiar with, other than our own, are via-last copper. I think they are also conformal, but I could be wrong. This makes them look like the Oki sensor."

So in general, the consensus is that as long as the via formation occurs after the metallization layers, as in via last for CIS, or certain interposer applications, a conformal via is fine. Otherwise, the via should be filled with something: copper, tungsten, or polymer. Got it. -- F.v.T.

A final (?) word on filling TSVs

Now look what I’ve started. After posting Bob Patti’s solution for performing UBM with conformal TSVs, I got a phone call from a 25 year industry veteran who prefers not to be identified, but who disagreed with Bob’s response. He maintains that when forming TSVs in a via-first approach for the purpose of silicon interposers, they must be either completely filled with copper, or lined with copper and filled with either a polymer material or solder, because if you attempt to put a redistribution layer or UBM layer on without filling them, “all the junk” will fill the via. He also noted that in the case of via-last formation for CMOS image sensor applications, there is no need to completely fill the via. I forgot to ask him if the same applies with DRAM memory stacks, which is Tezzaron’s area of specialty, so I’m thinking we may not have heard the last of this discussion.

Although a purely coincidental happenstance, yesterday’s debate turns out to be the ideal lead-in for my next announcement. Beginning July 6, and running through July 24th I will be moderating the BrightSpots 3D IC Forum, hosted by MCA Public Relations in cooperation with SemiNeedle, which will enable industry professionals to participate in an active discussion exploring the key issues surrounding 3D ICs from design to manufacture. The online round-table format offers a platform for continuous dialogue that extends the life of a traditional panel event and features a panel of industry experts ready to discuss critical issues associated with 3D IC technology initiated by questions from the public. To join the online discussion or log on to monitor progress, visit www.semineedle.com/MCA3DIC. You can also monitor BrightSpots-related activities on Twitter under the hash tag: #MCA3DIC. I’m very excited to be a part of this event, and look forward to covering it on my blog. – F.v.T.

TSV copper fill: is it necessary for UBM?

In response to a recent post about the whether/when it is necessary to completely fill TSVs, or sufficient to line them, I received an inquiry from Dr. Zhang of IME, where he has been researching with TSV formation for 2 ½ years. According to Zhang, he hasn’t been able to build reliable vias without completely filling them (either with all copper or copper liner + polymer or other materials). He cited an illustration from a paper he co-authored for ECTC 2009, titled Package Development of Through Silicon Via (TSV) Interposer Technology for Large Die (21x21mm) Fine-pitch Cu/low-k FCBGA (proceedings pp. 305-312) which demonstrates that it is necessary to completely fill the vias in order to perform front- and back-side metallization/UBM (under bump metallurgy). The example shown here is performed for a TSV interposer application.

Zhang inquired how it is possible to do front-side and back-side metallization/UBM without filling the vias. As I am an industry journalist and not a research scientist, I decided to pose the question to my readership, both to help Dr. Zhang further his research, and also to help create the atmosphere of interactivity I’m hoping to inspire with this blog.

If any of you can provide an answer to this question, please let me know, and I’ll post the response here. – F.v.T

More about UBM for conformal TSVs

In response to the previous post, Bob Patti of Tezzaron Semiconductors weighed in with a solution to performing under bump metallization (UBM) on conformal (lined rather than filled) TSVs. Patti says that Dr. Zhang is correct in stating that you can't put UBM on top of a conformal TSV. However, he suggests solving the issue by placing a pad next to the TSV and putting the UBM there. Thanks for your help, Bob! - F.v.T.